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WO/2024/095108A1 |
Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device comprises: a first insulator on a substrate; a second insulator on the first insulator; a third insulator on the second insulator;...
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WO/2024/095458A1 |
A first selective growth mask (103) formed on a first semiconductor layer (102) has a frame shape provided with a rectangular first opening (103a) in a planar view. A region of the first opening (103a) is a region in which an element is ...
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WO/2024/092544A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a depletion mode device, and an enhancement mode device. The second nitride-based semiconductor layer is...
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WO/2024/092440A1 |
The present application provides a display substrate, comprising: a base substrate; and a metal conductive layer located on one side of the base substrate. The metal conductive layer comprises: a core conductive layer and a functional co...
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WO/2024/097110A1 |
A method of forming a semiconductor device includes etching a semiconductor layer to form a plurality of mesa stripes in the semiconductor layer. The plurality of mesa stripes extend in a first direction and include mesa sidewalls that e...
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WO/2024/096070A1 |
A vertical-type semiconductor device equipped with a semiconductor substrate (10) which has a cell region (1) in which a semiconductor element is formed and a peripheral region (2) which surrounds the cell region (1), wherein: the cell r...
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WO/2024/045864A9 |
Provided in the present application are a semiconductor device, a preparation method and an electronic device. The method comprises: forming, on a substrate, a plurality of stacked structures, which are arranged spaced apart from each ot...
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WO/2024/095109A1 |
Provided is a semiconductor device having reduced power consumption. Or, provided is a semiconductor device having high reliability. Or, provided is a semiconductor device in which increases in circuit layout area are suppressed. Or, pro...
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WO/2024/095639A1 |
[Problem] To provide a light receiving element in which random noise is reduced. [Solution] A light receiving element according to an aspect of the present disclosure comprises a photoelectric conversion circuit that outputs a pixel sign...
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WO/2024/010848A3 |
A device includes a substrate and a ferroelectric layer supported by the substrate. The ferroelectric layer includes an alloy of a III-nitride material. The alloy includes a Group IIIB element. The substrate includes silicon.
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WO/2024/092543A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etching stop layer, a gate electrode, and a gate isolation layer. The second nitride-based semic...
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WO/2024/097722A1 |
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that includes a vertical bit line, a first semiconductor layer surrounding a first portion of the vertical b...
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WO/2024/095580A1 |
The present disclosure discloses a semiconductor device comprising a plurality of epitaxial layers including a barrier layer and a channel layer such that two-dimensional carrier densities are formed at an interface of the barrier layer ...
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WO/2024/093171A1 |
Provided in the present disclosure are a thin film transistor and a manufacturing method therefor, a display substrate, and a display apparatus. The thin film transistor comprises: a gate electrode, an active layer, a source electrode an...
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WO/2024/092720A1 |
The semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a dielectric layer, and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride...
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WO/2024/096966A1 |
In accordance with an aspect of the disclosure, a method of forming a heterostructure includes providing a metal layer of the heterostructure, the metal layer being supported by a substrate, implementing a surface treatment procedure to ...
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WO/2024/095110A1 |
Provided is a semiconductor device that can be miniaturized or highly integrated. The present invention includes first to third transistors and first to fourth insulating layers. The first transistor has first to third conductive layers,...
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WO/2024/096487A1 |
The present invention relates to a method for manufacturing a semiconductor device using a semiconductor growth template, and to a method for manufacturing a semiconductor light-emitting device or a power semiconductor device by using a ...
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WO/2024/092419A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a source field plate, a drain field plate, and a reduced surface ...
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WO/2024/095578A1 |
This semiconductor device 1 is provided with: a plurality of trench gates 50 which are positioned in an IGBT region 20A; a plurality of first dummy trenches 60 which are positioned in a diode region 20B; and a plurality of second dummy t...
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WO/2024/095113A1 |
Provided is a semiconductor device that is easily miniaturized. Provided is a semiconductor device with reduced parasitic capacitance. This semiconductor device includes a transistor, first and second insulating layers, and wiring. The t...
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WO/2024/095640A1 |
This silicon carbide substrate has a main surface, and contains vanadium and at least one element that is selected from among nitrogen, boron and aluminum. The main surface comprises a center, a first position, a second position, a third...
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WO/2024/091414A1 |
Gate-all-around transistor devices and methods for manufacturing the same are provided. The semiconductor device includes a substrate. The substrate includes a plurality of isolation regions formed in the substrate, the plurality of isol...
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WO/2024/092072A1 |
The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adj...
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WO/2024/086913A1 |
A module has two portions, each portion has two units provides an analog-type attenuator-tuning approach having digital control. Each of the units includes an input, an output, three selectable conductive paths, and an input switching el...
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WO/2024/087514A1 |
A semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate (100), a gate structure (200) and a channel region (300), wherein the substrate (100) comprises a gate trench (110). The cha...
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WO/2024/091179A1 |
This document describes a vertical channel-all-around metal-antiferroelectric-metal-insulator-semiconductor (MAMIS) field effect transistor and a method for manufacturing the same. This application also relates to a semiconductor device ...
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WO/2024/089963A1 |
The present invention provides a method for filling up a trench, which is formed in a silicon substrate and has a small opening width and a large aspect ratio, by means of high-rate epitaxial growth, while preventing closing of the openi...
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WO/2024/091606A1 |
Provided herein are methods and systems for subharmonic tags including a single antenna having a reactive input impedance and a set of lumped components coupled to the antenna, the lumped components having a frequency-dependent input imp...
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WO/2024/087174A1 |
The embodiments of the present disclosure provide a thin film transistor device and a manufacturing method therefor, a compound etching solution, and an array substrate. The method comprises: forming an active structure material layer co...
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WO/2024/089570A1 |
Provided is a new semiconductor device. This semiconductor device has: a memory cell circuit having a first transistor and a capacitive element; and a read-out circuit having a second transistor and a third transistor. An element layer i...
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WO/2024/087955A1 |
A semiconductor device and a manufacturing method therefor, the semiconductor device comprising: a substrate (1); a semiconductor layer (2) provided on the substrate (1) and comprising a first semiconductor lamination layer and a second ...
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WO/2024/092176A1 |
An enhanced edge termination structure for use in a charge balanced semiconductor device is provided. The edge termination structure includes a plurality of edge termination trenches and a plurality of semiconductor mesa regions, each of...
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WO/2024/087189A1 |
Disclosed in the present application are an anti-radiation field effect transistor device and application thereof in an anti-radiation environment, which are used for solving the problem in the prior art of an anti-radiation method for a...
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WO/2024/091302A1 |
A semiconductor structure includes a stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer includes silicon having carrier dopants, and each cap...
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WO/2024/087713A1 |
A display panel and a display device. The display panel further comprises a substrate (10), a shielding layer (20), and a driving circuit layer (30); the shielding layer (20) is arranged on the substrate (10); the driving circuit layer (...
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WO/2024/091487A1 |
Disclosed is a technique for transporting and arranging electronic components, using an optical system utilizing a laser beam to produce an optical trap in a fluid near a target site of a backplate, where a primary optical axis of the la...
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WO/2024/091422A1 |
A three-dimensional (3D) dynamic random-access memory (DRAM) includes a substrate and a plurality of nanosheet transistors stacked vertically on a surface of the substrate. Each of the nanosheet transistors comprises a gate, a source, an...
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WO/2024/087188A1 |
Disclosed in the present application is a field effect transistor device having a blocking region, which device is used for alleviating the problem in the prior art of a short-channel effect of a field effect transistor. The field effect...
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WO/2024/090370A1 |
According to the present disclosure, it is possible to achieve a magnetic domain wall moving element capable of improving a magnetic domain wall moving speed. A magnetic domain wall moving element according to one embodiment of the prese...
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WO/2024/090117A1 |
A semiconductor substrate (11) comprises an FS layer (13) between a collector layer (12) and a drift layer (14). A total dose amount of the collector layer (12) is less than 1×1013/cm2. The collector layer (12) has a plurality of peaks ...
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WO/2024/090243A1 |
A semiconductor device (1) is provided with, in plan view: a transistor (10) formed in a first region (A1) of a semiconductor layer (40); a transistor (20) formed in a second region (A2) adjacent to the first region (A1) of the semicondu...
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WO/2024/092179A1 |
A semiconductor device is provided that includes an epitaxial layer disposed on a semiconductor substrate, the epitaxial layer including an active region, in which at least one active element is formed, and an edge termination region, in...
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WO/2024/087703A1 |
Provided in the present application are a transistor, an integrated circuit and a preparation method, and an electronic device. The transistor comprises a channel and a gate arranged on the channel. The gate comprises a coverage layer ar...
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WO/2024/087634A1 |
The present application relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: an isolation tray (118) having a first conductivity type; an injection assistance structure comprisi...
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WO/2024/090081A1 |
[Problem] To provide an amplifier circuit, a comparator, and a solid-state imaging device that can suppress RTS noise. [Solution] An amplifier circuit according to the present disclosure comprises: an active load; and a plurality of inpu...
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WO/2024/089571A1 |
Provided is a semiconductor device having favorable electrical properties. This semiconductor device has a transistor, a first interlayer insulating layer, and a second interlayer insulating layer on the first interlayer insulating layer...
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WO/2024/085097A1 |
[Problem] When a magnetic field detection element is formed on an Si substrate, reducing the coil pitch inside an inverted-trapezoidal groove makes it easier for the step at an upper part of the groove or the edge of a bottom surface of ...
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WO/2024/085528A1 |
The present invention relates to a thin-film transistor and a manufacturing method therefor. The thin film transistor comprises: a gate electrode; an active layer spaced apart from the gate electrode; a source electrode provided on one s...
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WO/2024/086458A1 |
A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each ga...
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