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WO/2023/245658A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a third nitride-based semiconductor layer, and a fourth nitri...
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WO/2023/249538A1 |
A semiconductor device, comprising: a substrate (1) of a first conductivity type that is a base for the semiconductor device; a high voltage junction field effect transistor, JFET, over the substrate (1), wherein the JFET comprising a pl...
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WO/2023/245787A1 |
Disclosed in the present disclosure are a semiconductor structure manufacturing method, and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate; forming a laminated structure on th...
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WO/2023/249845A1 |
A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and ver...
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WO/2023/248702A1 |
The present invention relates to a nitride semiconductor wafer comprising a silicon-based substrate, a buffer layer that comprises a nitride semiconductor and is laminated on the silicon-based substrate; and a functional layer that inclu...
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WO/2023/248050A1 |
A qubit system for quantum computing includes a semiconductor structure, an array of plunger gates, and an array of magnetic structures. The array of gates is above the semiconductor structure forming a linear one-dimensional (1D) array ...
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WO/2023/249486A1 |
Embodiments in this disclosure relate to a quantum dot structure comprising a two-dimensional quantum dot array and a micromagnet array comprising a plurality of micromagnets arranged in a periodic micromagnet configuration. The pluralit...
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WO/2023/248287A1 |
According to the present disclosure, in order to enable evaluation of a semiconductor on the basis of characteristics that are equivalent to transistor (Tr) characteristics and are acquired in an earlier stage during a semiconductor manu...
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WO/2023/249847A1 |
A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches ar...
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WO/2023/245759A1 |
Embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. The semiconductor structure comprises a substrate and a device structure layer arranged on the substrate. The device structure lay...
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WO/2023/247748A1 |
This disclosure relates to semiconductor devices for integrated devices like nanosheet devices, forksheet devices, or complementary field effect transistor devices. The semiconductor device comprises a substrate layer (101, 102) and a se...
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WO/2023/248753A1 |
This gallium nitride-based semiconductor device comprises: an amorphous substrate; an orientation control layer on the amorphous substrate; a gallium nitride-based semiconductor layer on the orientation control layer; and at least one el...
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WO/2023/247545A1 |
The present disclosure relates to a manufacturing method for a power semiconductor device (20), comprising: forming at least one insulating layer (3) on a surface (2a) of a crystalline growth substrate (2), the at least one insulating la...
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WO/2023/245697A1 |
Disclosed in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises a substrate, a plurality of oxide pillars, a plurality of activ...
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WO/2023/248643A1 |
Provided is a display device having a laminate structure provided with a light-emitting element that changes in luminance in accordance with a supplied current, a current source transistor that is electrically connected to a current sour...
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WO/2023/247117A2 |
According to an embodiment, the method comprises a step of providing a semiconductor body (1) with a top side (10). A mask (2) is applied on the top side of the semiconductor body, wherein the mask comprises at least one first section (2...
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WO/2023/248418A1 |
This memory device having, on a substrate in a plan view, a plurality of pages which are each formed by a plurality of memory cells arrayed in the row direction and which are arrayed in the column direction is characterized in that: the ...
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WO/2023/245756A1 |
Embodiments of the present disclosure provide a semiconductor structure and a method for forming same. The method comprises: providing a substrate, wherein the substrate comprises double heterostructures arranged in an array in a first d...
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WO/2023/248648A1 |
The present invention improves reliability. This semiconductor device comprises: an island-shaped semiconductor section having a first portion and a second portion that is provided side by side with the first portion in the first directi...
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WO/2023/241794A1 |
The semiconductor device (100) is a vertical IGBT and comprises a semiconductor body (1) with a top side (10), a main electrode (2) on the top side and a gate electrode (3). The semiconductor body comprises a drift layer (11) of a first ...
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WO/2023/241772A1 |
The present disclosure relates to a semiconductor device. The semiconductor device comprises:a substrate comprising a first wide-bandgap semiconductor material; a first region of a first conductivity type and a second region of a second ...
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WO/2023/243189A1 |
Provided is a semiconductor device manufacturing method by which it is possible to reduce the width of a termination region and suppress the electrical field concentration in the termination region. The semiconductor device manufacturing...
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WO/2023/241433A1 |
A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the...
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WO/2023/240491A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first electrode and a second electrode, a gate electrode, a passivation layer, and a field plate. The ...
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WO/2023/240529A1 |
Some embodiments of the disclosure provide a semiconductor device. The semiconductor device comprises: a substrate; a first nitride semiconductor layer on the substrate; a second nitride semiconductor layer on the first nitride semicondu...
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WO/2023/243537A1 |
A semiconductor device 1 according to the present invention comprises a semiconductor substrate 10, a first electrode 20, and an insulating layer 30, wherein the semiconductor substrate 10 has: a first semiconductor region 12 of a first ...
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WO/2023/240752A1 |
The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a s...
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WO/2023/242994A1 |
A semiconductor device (101) comprises: a nitride semiconductor layer (10) that has a first main surface (51), and a second main surface (52) on the reverse side from the first main surface (51); and a diamond layer (11) that has a third...
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WO/2023/245205A1 |
The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a ...
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WO/2023/242991A1 |
The present disclosure relates to a power semiconductor device in which the main current flows in the thickness direction of a semiconductor substrate, wherein the semiconductor substrate has a first active region which is provided in th...
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WO/2023/243470A1 |
This wafer structure includes: a wafer having a first surface on one side and a second surface on the other side; a first electrode covering the first surface; a second electrode covering the inner part of the second surface such that a ...
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WO/2023/244489A1 |
Bifunctional graphene dielectrophoresis (DEP)-graphene field effect transistor (GFET) devices are provided. Aspects of the devices include: a graphene dielectrophoresis (DEP) component and a graphene field effect transistor (GFET) compon...
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WO/2023/241070A1 |
The present application relates to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a first metal layer, which is arranged on a substrate; a dielectric layer, which is arranged on the side o...
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WO/2023/243245A1 |
In the present invention, a semiconductor device comprises a gallium-containing first nitride semiconductor layer, and a gallium-containing second nitride semiconductor layer that is formed on the first nitride semiconductor layer, the s...
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WO/2023/243073A1 |
In a transistor (1) according to the present disclosure, the quantity of boron ions (B+) that are implanted in a gate insulating film (5) is greater than the quantity of boron ions (B+) that are implanted in a first region (4b) and a sec...
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WO/2023/244954A1 |
A semiconductor device (200) is described herein. The semiconductor device comprises a silicon substrate layer (204). The semiconductor device comprises a first semiconductor layer comprising a gallium nitride layer (206), the first semi...
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WO/2023/243882A1 |
Disclosed are a silicon carbide based-lateral power semiconductor device, and a method for manufacturing same. The silicon carbide-based lateral power semiconductor device includes: a substrate of a first conductivity type made of silico...
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WO/2023/242953A1 |
The present disclosure pertains to a semiconductor device and a method for manufacturing same, and the purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing same, with which the outermost s...
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WO/2023/243556A1 |
A field effect transistor (10) according to the present invention is provided with: an electron transit layer (26); an electron supply layer (28) which is arranged on the electron transit layer so as to generate a two-dimensional electro...
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WO/2023/241925A1 |
A microelectronic structure including a stacked transistor having a lower transistor (112) and an upper transistor (127). A shared contact (230) in contact with a lower source/drain (160) of the first lower transistor and an upper source...
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WO/2023/241593A1 |
The embodiments of the present application relate to the technical field of semiconductors. Provided are a radio frequency semiconductor device, an electronic device, and a preparation method for a radio frequency semiconductor device. A...
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WO/2023/244222A1 |
A double-channel semiconductor device is presented herein. The double-channel semiconductor device is a cascode solution integrating two semiconductor channels: a HEMT channel (104) and a thin film transistor (TFT) channel (216). The HEM...
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WO/2023/242664A1 |
Provided is a semiconductor device having favorable electrical characteristics. This semiconductor device has: a first layered body; a semiconductor layer having a channel-forming region under the first layered body; and a second layered...
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WO/2023/241586A1 |
A display substrate and a preparation method therefor, and a display panel. The display substrate comprises: a base substrate (21); a metal conductive layer, which is located on one side of the base substrate (21) and comprises a plurali...
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WO/2023/236373A1 |
Disclosed herein are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises a first source/drain layer (1); a second source/drain layer (3); an insulating layer (2), which...
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WO/2023/240020A1 |
A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer, source and drain contacts on the semiconductor structure, and a conductive element in a recess in the barrier layer between the source...
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WO/2023/237561A1 |
The present invention provides a graphene-containing laminate comprising, in order: a substrate; a graphene layer structure; a first metal oxide layer formed of a first metal oxide, wherein the first metal oxide is a transition metal oxi...
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WO/2023/236375A1 |
Disclosed are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises: a second source/drain layer (2), an insulation layer (3) and a first source/drain layer (1), which ar...
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WO/2023/236272A1 |
Disclosed in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate, first gate electrode structures and second gate electrode struct...
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WO/2023/237961A1 |
This semiconductor device (200) includes: an oxide (230) on a substrate; a first conductor (242a1) and a second conductor (242b1) that are on the oxide and are separated from each other; a third conductor (242a2) that is in contact with ...
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