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WO/2024/033742A1 |
The present invention provides a novel signal output circuit. The present invention provides a shift register which has a signal output circuit that comprises a vertical channel transistor. The present invention enables the achievement o...
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WO/2024/035471A1 |
A monolithic 3D complementary field-effect transistor (FET) (CFET) circuit includes a first CFET structure (102A) and a second CFET structure (102B) in a logic circuit within a device layer (108). A first interconnect layer (112) dispose...
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WO/2024/035496A1 |
A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the inte...
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WO/2024/034807A1 |
The present invention discloses a semiconductor layer containing amorphous tellurium oxide, a thin film transistor (TFT) including same, and a fabrication method therefor. The semiconductor includes: a chalcogen atom containing at least ...
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WO/2024/033185A1 |
The invention relates to a method for determining a simulation model for a power diode (108), more particularly a gallium oxide power diode, the method comprising a step of executing a basic model for the power diode (108) in order to ob...
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WO/2024/034932A1 |
A display device of the present invention comprises: a base layer; a circuit layer which is disposed on the base layer and comprises a [1-1]th pixel circuit and a [1-2]th pixel circuit; and a light-emitting element layer which is dispose...
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WO/2024/029001A1 |
The present invention suppresses a leak current. This semiconductor device comprises: a first anode electrode provided in a portion of an upper surface of a gallium oxide layer of a first conductor type; a semiconductor layer of a second...
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WO/2024/029237A1 |
A semiconductor device according to the present invention comprises: a well region which is formed in a surface part of a first main surface of a semiconductor layer; a source region which is formed in a surface part of the well region; ...
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WO/2024/029438A1 |
This oxide semiconductor film is provided on a substrate and includes a plurality of crystal grains. The oxide semiconductor film includes indium (In), and a first metal element selected from the group consisting of aluminum (Al), galliu...
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WO/2024/026816A1 |
A nitride-based semiconductor device includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a group III oxide layer, and a gate electrode. The second III-V nitride-based semiconductor ...
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WO/2024/026597A1 |
A nitride-based semiconductor deviceincludes a first and a second nitride-based semiconductor layers, a source and a drain electrodes, a doped nitride-based semiconductor layer, and a gate electrode. The source electrode is disposed over...
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WO/2024/026928A1 |
The present disclosure relates to a preparation method for a semiconductor structure, and the semiconductor structure. The method comprises: providing a substrate, and forming on the substrate an initial stacked structure that comprises ...
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WO/2024/028682A1 |
Provided is a semiconductor device that demonstrates fast access speed. This semiconductor device has a first storage layer, a second storage layer, and a circuit layer. The first storage layer has a plurality of first storage circuits, ...
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WO/2024/029282A1 |
This semiconductor testing apparatus comprises: a first node to which one end of a semiconductor switching device is electrically connected; a second node to which the other end of the semiconductor switching device is electrically conne...
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WO/2024/027964A1 |
The invention relates to a semiconductor component (2). The semiconductor component (2) comprises a circuit carrier (S) having a first conductor layer (CU1), in which a first conductor path (F1) is formed. The semiconductor component (2)...
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WO/2024/030127A1 |
A high electron mobility transistor (HEMT) which includes a source disposed on a surface, a drain disposed on the surface, a gate disposed on the surface between the source and the drain, and a first field plate disposed on the surface b...
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WO/2024/029398A1 |
A semiconductor device (10) comprises: a semiconductor layer (14) including a peripheral region (40) and an inner region (42); a gate wire (44); and a source wire (34). A plurality of peripheral gate fingers (46) of the gate wire (44) ar...
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WO/2024/026933A1 |
The embodiments of the present disclosure provide a semiconductor structure and a formation method therefor. The method comprises: providing a substrate, wherein the substrate comprises a first area and a second area located outside the ...
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WO/2024/026936A1 |
Embodiments of the present disclosure relate to a memory structure, a semiconductor structure, and a preparation method therefor. The semiconductor structure comprises: a substrate, an isolation structure being provided in the substrate,...
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WO/2024/030259A1 |
An apparatus, in accordance with one aspect of the present invention, includes a superjunction device having a voltage sustaining layer formed of a semiconductor material and a dopant in the voltage sustaining layer. The dopant is for di...
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WO/2024/026904A1 |
The present invention relates to the technical field of semiconductors, and relates to a preparation method for and a structure of a low-voltage super-junction trench MOS device. The preparation method comprises: Step S1, forming an epit...
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WO/2024/029181A1 |
This transistor includes: an amorphous substrate; a first buffer layer on the amorphous substrate; a first nitride semiconductor layer that is provided in an island shape on the first buffer layer; a second nitride semiconductor layer th...
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WO/2024/027333A1 |
Disclosed are a semiconductor structure and a method for forming same. The semiconductor structure comprises: a substrate and a plurality of semiconductor pillars. Each semiconductor pillar is provided with a channel region and doped reg...
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WO/2024/028996A1 |
The purpose of the present invention is to provide a technology capable of increasing surge resistance in a silicon carbide semiconductor device in which an SBD is embedded. A silicon carbide semiconductor device comprises a first conduc...
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WO/2024/029429A1 |
This laminate structure has an underlying insulating layer, a metal oxide layer disposed on the underlying insulating layer, and an oxide semiconductor layer disposed in contact with the metal oxide layer. The oxide semiconductor layer h...
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WO/2024/028681A1 |
The present invention provides a semiconductor device which is capable of achieving miniaturization or high integration. A semiconductor device according to the present invention comprises: a first conductor and a second conductor, which...
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WO/2024/026916A1 |
Disclosed in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a source doped region, a drain doped region, and a lightly doped region and a...
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WO/2024/026967A1 |
A semiconductor structure and a preparation method therefor. The method comprises: providing a substrate (1), wherein an isolation trench (11) is formed in the substrate; forming a first isolation layer (21) in the isolation trench, wher...
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WO/2024/027357A1 |
The present disclosure relates to a field-stop insulated gate bipolar transistor and a manufacturing method therefor. The field-stop insulated gate bipolar transistor comprises a drift region, a front surface structure and a back surface...
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WO/2024/029437A1 |
This thin-film transistor comprises: a substrate; a metal oxide layer provided on the substrate; an oxide semiconductor layer that is provided in contact with the metal oxide layer and that contains a plurality of crystal grains; a gate ...
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WO/2024/028995A1 |
A semiconductor device and a power conversion device according to the present disclosure each comprise: a drift layer (20) of a first conductivity type; a gate electrode (60) which is arranged so as to face a well region (30) of a second...
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WO/2024/029153A1 |
The present invention provides an IGBT wherein an IE effect is achieved, while suppressing latch-up. The present invention provides an insulated gate bipolar transistor which comprises a first active region (31), a second active region (...
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WO/2024/026738A1 |
The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a doped nitride-based semiconductor layer, a first gate elec...
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WO/2024/030802A1 |
Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer...
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WO/2024/024307A1 |
Provided is a fin-type field effect transistor 1 comprising: a semiconductor layer 10 made of a gallium oxide based semiconductor and having a plurality of fins 120; a gate electrode 14 formed on the side surface of each of the plurality...
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WO/2024/025251A1 |
The present invention relates to a method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device, according to one embodiment, may comprise the steps of: laminating a plurality of insulating layers an...
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WO/2024/026279A1 |
Lateral III-N devices such as AlGaN/GaN HEMTs can have structures which serve to improve performance and reduce current degradation. The III-N device can include a conductive substrate and a III-N material structure that includes a III-N...
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WO/2024/024386A1 |
This semiconductor device 10 comprises a substrate 12 made from silicon carbide, and a first-electroconductivity-type semiconductor layer provided on a first surface 12a of the substrate 12. A high-hydrogen-concentration region 40 in whi...
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WO/2024/024374A1 |
A semiconductor device (1) comprising: a semiconductor substrate (201) having a semiconductor element (2) configured thereon; a first electrode (231) and a second electrode (232), both disposed on one surface (22) of the semiconductor el...
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WO/2024/024415A1 |
This semiconductor device comprises: a field plate which is disposed on a semiconductor layer between a drain region and a source/gate region, and which is spirally wound a plurality of times in a plan view, the field plate being resisti...
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WO/2024/023397A1 |
The present invention relates to an electronic device (1) comprising a silicon-on-insulator strip (100) laterally defined by insulating trenches (106); a first gate (112) supported by the strip; a second gate (114), or a third gate (116)...
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WO/2024/021336A1 |
Disclosed in the present application is a non-uniformly doped field effect transistor device, which is used for solving the problem of the short-channel effect of a field effect transistor in the prior art. The field effect transistor de...
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WO/2024/024497A1 |
A storage device according to an aspect of the present disclosure comprises: a magnetoresistive storage element that changes into at least four distinguishable resistance states; and a writing unit that changes the magnetoresistive stora...
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WO/2024/023603A1 |
A microelectronic structure comprises a first stacked device structure comprising a first upper device and a first lower device, a second stacked device structure comprising a second upper device and a second lower device, and an isolati...
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WO/2024/021154A1 |
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: an active pillar, the active pillar comprising...
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WO/2024/021977A1 |
Disclosed in the present application are a trench-gate power MOSFET. The trench-gate power MOSFET comprises: a base, which is a base provided with a wide-bandgap semiconductor of a first conductivity type; an epitaxial layer, which is gr...
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WO/2024/024073A1 |
This semiconductor device comprises second-conductive-type first pillar regions (13) that are formed below a plurality of gate trenches (6) in which gate electrodes (8) are embedded, and first-conductive-type second pillar regions (14) t...
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WO/2024/024822A1 |
This semiconductor device (1) comprises: a Si substrate (101); a reverse-surface electrode (304) provided to the lower side of the Si substrate (101); an SiC layer (102) provided to the upper side of the Si substrate (101); a nitride sem...
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WO/2024/025561A1 |
A wireless front-end can include a plurality of circuits, including a power amplifier (PA), a low noise amplifier (LNA), and an RF switch. In order to decrease the size and improve the performance of the front-end, the various circuits o...
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WO/2024/021337A1 |
The present application discloses a field effect transistor device having a blocking region, for use in solving the problem of short-channel effects of field effect transistors in the prior art. The field effect transistor device compris...
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