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WO/2024/075923A1 |
A thin film transistor, a transistor array substrate comprising same, and a method for manufacturing the transistor array substrate, are provided. The thin film transistor comprises: a substrate; an active layer disposed on the substrate...
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WO/2024/075391A1 |
This nitride semiconductor device (10) comprises: a hexagonal SiC substrate (22) having a main surface (22A) inclined at an off angle of 2-6° in a specific crystal direction with respect to the c-plane; a nitride semiconductor layer (24...
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WO/2024/074969A1 |
Provided is a storage device which can be miniaturized and made highly integrated. This storage device has a configuration having a capacitive element formed directly below a vertical transistor, wherein one electrode of the capacitive e...
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WO/2024/072806A1 |
A fabrication method of a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride-oxide (ONO) stack over a substrate in an in-situ atomic layer deposition (ALD) tool or chamber. Radical oxid...
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WO/2024/065148A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, an etch resistant layer, and a gate electrode. The second nitr...
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WO/2024/069340A1 |
The present invention provides a semiconductor device which comprises a transistor of a very small size. This semiconductor device comprises first and second transistors; the first transistor comprises first to third conductive layers, a...
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WO/2024/070915A1 |
The purpose of one aspect of the present invention is to provide a resin that has liquid repellency and high solubility in alkaline solution, the resin being rendered insoluble in solvents through photocrosslinking at a low exposure leve...
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WO/2024/067997A1 |
In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein - the semiconductor body (2) comprises a first region (21) which is a source region or an emitt...
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WO/2024/066369A1 |
A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. ...
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WO/2024/065110A1 |
The present application relates to the technical field of display, and discloses a thin film transistor and a preparation method, and a display panel. Since the concentration of hydrogen in a semiconductor layer of the thin film transist...
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WO/2024/068453A1 |
Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of ...
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WO/2024/070392A1 |
The present invention provides a semiconductor device that comprises: an insulating first film which is formed along the side wall of an element isolation trench, and which has a first portion that is formed along the bottom wall and the...
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WO/2024/073358A1 |
Embodiments of the present disclosure provide devices, apparatuses, and methods related to FETs with reduced leakage. In some embodiments, devices on a silicon-on-insulator substrate may include a silicon layer; a gate structure at least...
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WO/2024/070021A1 |
Provided is a semiconductor device that, with respect to a trench MOSFET having a vertical channel fin structure, is capable of improving the short circuit tolerance and reducing the gate capacity while maintaining a high channel density...
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WO/2024/073632A1 |
A microelectronic device (100) includes a buried trench capacitor (170) below an electronic component (174) of the microelectronic device (100). In one embodiment, the buried trench capacitor (170) may be formed between a silicon oxide c...
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WO/2024/066567A1 |
Embodiments of the present application relate to the technical field of semiconductors, and provide a semiconductor structure and a manufacturing method therefor, and an electronic device, for use in further improving the electron mobili...
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WO/2024/065149A1 |
A nitride-based semiconductor device (1A) includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a gate dielectric layer (16), and a gate electrode (40). The second III-V nitride-based...
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WO/2024/067197A1 |
A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first re...
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WO/2024/066745A1 |
A HEMT device, comprising a semiconductor layer, at least one gate structure, a first insulating layer (210), a dotted drain contact through hole (211), an annular source contact through hole (212), a drain ohmic contact metal layer (215...
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WO/2024/067998A1 |
In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein - the semiconductor body (2) comprises a first region (21) which is a source region or an emitt...
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WO/2024/070344A1 |
The present invention improves electrical characteristics. A capacitor (1) comprises a silicon substrate (2), a dielectric layer (4), and a conductor layer (5). The silicon substrate (2) has a doped layer (3). The doped layer (3) include...
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WO/2024/065310A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, and at least one electrode structure. The second nitride-based semiconductor layer is disposed on the fi...
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WO/2024/069733A1 |
According to the present invention, a method for manufacturing a magnetized rotary element has a measurement step, a comparison step, and a determination step. In the measurement step, a laminate comprising a first detection layer and a ...
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WO/2024/069339A1 |
This storage device has: a first insulator on a substrate; an oxide semiconductor which covers at least a portion of the first insulator; first and second conductors on the oxide semiconductor; a second insulator on the first conductor; ...
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WO/2024/065176A1 |
An array substrate, a display panel, and a method for manufacturing an array substrate. The array substrate comprises: a base substrate (1); a first active layer (2) on the base substrate (1); a second active layer (3) on the side of the...
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WO/2024/070164A1 |
A semiconductor device comprising: a chip having a main surface and made of a semiconductor of a first conduction type; a first region of a second conduction type selectivity formed in a main-surface-side surface-layer portion of the chi...
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WO/2024/060259A1 |
The present application discloses a semiconductor device and a preparation method therefor, a power conversion circuit, and a vehicle. The semiconductor device comprises: an N-type semiconductor substrate, an epitaxial layer, a trench st...
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WO/2024/060811A1 |
The present invention provides a power MOSFET and a manufacturing method therefor. The power MOSFET comprises a semiconductor structure, gate structures, source trench structures, a body region, source regions, contact regions, a barrier...
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WO/2024/063517A1 |
The present invention provides a display device comprising: a first electrode and a second electrode, which are arranged on a substrate so as to be distanced from each other; a first insulating layer, which is arranged on the substrate a...
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WO/2024/060211A1 |
A thin-film transistor and a manufacturing method therefor, and an array substrate and a display apparatus. The thin-film transistor comprises an active layer and an electrode layer, wherein the active layer comprises a channel region, a...
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WO/2024/060046A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, and a first dielectric layer. The second nitride-based semiconductor layer is disposed...
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WO/2024/063901A1 |
Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include cells that form inverter devices, NAND devices, and MUX (multiplexe...
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WO/2024/063886A1 |
A cell layout that implements stacked transistors is disclosed. The cell layout utilizes both topside metal routing and backside metal routing. Various connection routes between components of the transistors (e.g., gates, sources, and dr...
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WO/2024/060261A1 |
The present application discloses a semiconductor device and a preparation method therefor, a power conversion circuit and a vehicle. The semiconductor device comprises: an N-type semiconductor substrate, an epitaxial layer, a trench str...
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WO/2024/062297A1 |
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first...
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WO/2024/060740A1 |
Provided in the embodiments of the present application is an IGBT device. The IGBT device comprises a collector electrode; an electric-field termination layer formed on the collector electrode; an electric-field transition layer formed o...
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WO/2024/064324A1 |
Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group ...
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WO/2024/060260A1 |
Disclosed in the present application are a semiconductor device, a preparation method, a power conversion circuit and a vehicle. The semiconductor device comprises: an N-type semiconductor substrate, a first epitaxial layer, a plurality ...
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WO/2024/060110A1 |
A nitride-based semiconductor device includes a first III-V nitride-based semiconductor layer, a second III-V nitride-based semiconductor layer, a source electrode and a drain electrode, and a doped nitride-based semiconductor layer. The...
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WO/2024/062789A1 |
This semiconductor device comprises: a first compound semiconductor; a first electrode arranged on the first compound semiconductor and connected to the first compound semiconductor by Schottky contact; a second compound semiconductor ar...
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WO/2024/060333A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure and a method for forming the same. The method comprises: providing a substrate, the substrate comprising active strips and first trenches extending in a ...
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WO/2024/064146A1 |
This application is directed to integrating metal oxide semiconductor (MOS) transistors and Schottky barrier diodes (SBDs). An integrated planar semiconductor device includes a substrate, an SBD joining an SBD semiconductor and a barrier...
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WO/2024/060083A1 |
Embodiments of the present application relate to the technical field of semiconductors, and provide a semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises a substrate, a c...
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WO/2024/061038A1 |
A super-junction LDMOS device and a method for manufacturing same. A super-junction LDMOS device (100) comprises: a substrate (20); an epitaxial layer (21), which covers the surface of one side of the substrate (20); a body region (28) a...
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WO/2024/061264A1 |
Embodiments of the present disclosure relate to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor body, comprising a substrate, a buried layer, and an epitaxial layer, wherein...
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WO/2024/064565A2 |
Vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. In exemplary aspects, to reduce contact resistance of the VCFET, an end portion of the vert...
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WO/2024/062978A1 |
A magnetoresistive element according to one embodiment of the present disclosure comprises a multilayer structure, a memory layer disposed on the multilayer structure and changeable in magnetization direction, a nonmagnetic layer dispose...
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WO/2024/063826A2 |
Embodiments relate to a transistor having a substrate and a gate formed in or on a surface of the substrate. The gate can include a piezoelectric material. The transistor has a drain and a source formed in or on a surface of the gate. Th...
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WO/2024/062256A1 |
A monolithic array of semiconductor devices on a wafer comprises a first semiconductor device occupying a first device area on the wafer above a first porous region in the wafer. The first porous region has a first structure, a first por...
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WO/2024/064145A1 |
This application is directed to integrating field-effect transistors (FETs) and Schottky barrier diodes (SBDs) on a substrate and forming an integrated and planar semiconductor device. A P-type Metal Oxide Semiconductor (PMOS) transistor...
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