| Document |
Document Title |
|
WO/2024/025945A1 |
Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etc...
|
|
WO/2024/021338A1 |
Disclosed in the present application is a field effect transistor device improved by means of equivalent source and drain regions, which is used for solving the problem of short channel effects of field effect transistors in the prior ar...
|
|
WO/2024/021151A1 |
The present application provides a semiconductor device and an electronic device. The semiconductor device comprises an insulating substrate and a thin film transistor layer. The thin film transistor layer comprises a first active layer ...
|
|
WO/2024/024475A1 |
A nitride semiconductor device (10) comprises: an electron transit layer (16) that is constituted by a nitride semiconductor; an electron supply layer (18) that is provided on the electron transit layer (16) and that is constituted by a ...
|
|
WO/2024/018924A1 |
This silicon carbide epitaxial substrate comprises a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is positioned on the silicon carbide substrate. The silicon carbide epitaxial layer...
|
|
WO/2024/018625A1 |
In this MEMS element, a backplate (7) including a fixed electrode (5) and a vibrating film (3) including a movable electrode, opposing each other across a spacer (4), are arranged on a substrate (1) provided with a back chamber (9). The ...
|
|
WO/2024/017136A1 |
The present invention provides a semiconductor device structure and a manufacturing method therefor. The semiconductor device structure comprises a substrate, a body region, a trench, a doped region, a gate structure, a source region, an...
|
|
WO/2024/019066A1 |
This information generation device comprises: a magnetic body; a magnetic field application part that applies a magnetic field to the magnetic body; and an information generation part that applies an alternating magnetic field to the mag...
|
|
WO/2024/018695A1 |
The present invention provides a semiconductor device which comprises a field plate that is connected to a guard ring, which is formed in a termination region, by the intermediary of a barrier metal layer, wherein it is possible to suppr...
|
|
WO/2024/018502A1 |
A spin element according to the present invention is provided with: a semiconductor layer (102) which is formed on a substrate (101); a source (103) and a drain (104), which are formed in the semiconductor layer (102) at a specific dista...
|
|
WO/2024/016920A1 |
A diode photovoltaic module, comprising a first electrode (1), a second electrode (2), a diode chip (3) and a connection structure, wherein the diode chip (3) is provided with a first mounting surface (31) and a second mounting surface (...
|
|
WO/2024/018749A1 |
This device 10, for which the dielectric constant can be negative, comprises a pair of electrodes 11 and 12, and a conductor 13 arranged between the pair of electrodes 11 and 12, wherein, when energized, the conductor 13 generates a tunn...
|
|
WO/2024/016753A1 |
A three-dimensional semiconductor structure and a forming method therefor. The forming method comprises: etching a stacked structure of a source region and a drain region, forming in the stacked structure of the source region and the dra...
|
|
WO/2024/018715A1 |
A semiconductor device (1) comprises: a semiconductor layer (40) that is rectangular in a plan view; a first vertical MOS transistor (10) formed in a first region (A1) of the semiconductor layer (40); and a second vertical MOS transistor...
|
|
WO/2024/016410A1 |
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a preparation method therefor. The semiconductor structure comprises: a substrate, the substrate comprising an active ...
|
|
WO/2024/016216A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a doped nitride-based semiconductor layer, a nitride-based isolation layer, a gate electrode, and a pass...
|
|
WO/2024/016440A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, which is provided with an ac...
|
|
WO/2024/018317A1 |
The present invention provides a semiconductor device that achieves both low power consumption and high performance. Provided is a semiconductor device having first and second transistors. The first transistor has a first conductive laye...
|
|
WO/2024/016219A1 |
A nitride-based semiconductor device includes a first nitride-based semiconductor layer (16), a second nitride-based semiconductor layer (18), a doped nitride-based semiconductor layer (20), a passivation layer (30), a first dielectric l...
|
|
WO/2024/018892A1 |
The present invention includes a substrate, and a semiconductor stacked structure disposed on the substrate. The semiconductor stacked structure includes: a multi-channel structure including a plurality of first nitride semiconductor lay...
|
|
WO/2024/016221A1 |
A nitride-based semiconductor device includes a nitride-based semiconductor wafer, a protecting layer, and a plurality of connecting bumps. The nitride-based semiconductor wafer comprises a plurality of nitride-based dies. Each of the ni...
|
|
WO/2024/014510A1 |
A SiC junction field effect transistor comprises: a SiC substrate 10; a first conduction-type channel region 11 that is formed on a main surface of the SiC substrate; a second conduction-type embedded gate region 14 that is formed below ...
|
|
WO/2024/012648A1 |
Power semiconductor device and method for producing a power semiconductor device The power semiconductor device (100) comprises a semiconductor body (1) with a top side (10), a main electrode (2) on the top side and a gate electrode (3) ...
|
|
WO/2024/014358A1 |
A silicon carbide substrate according to the present invention has a main surface. The main surface comprises: a central part; and an outer peripheral part that is positioned 10 mm away from the outer peripheral edge of the main surface ...
|
|
WO/2024/014362A1 |
This semiconductor device includes: a chip having a main surface; a trench resistor structure formed in the main surface; a resistor film that is formed on the main surface and is electrically connected to the trench resistor structure; ...
|
|
WO/2024/012428A1 |
The present application relates to a semiconductor device and a preparation method therefor. The semiconductor device comprises a semiconductor substrate (111), an insulating buried layer (112), a drift region (120), and a plurality of d...
|
|
WO/2024/015623A1 |
The present invention discloses a GaN trench MOSFET and its fabrication method. The GaN trench MOSFET of the current invention has an n-GaN region having both Mg and donor impurities below a trench bottom, extending to an n--GaN drift la...
|
|
WO/2024/011658A1 |
A display panel (100), comprising: providing a protruding structure (21) in a thin film transistor (2) of a non-display area (102), then providing a source/drain layer (25) on the protruding structure (21); a source electrode (251) and a...
|
|
WO/2024/015154A1 |
A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dim...
|
|
WO/2024/011609A1 |
A semiconductor device includes a substrate, an insulation layer, and a plurality of epitaxial structures. The substrate includes a first substrate layer and a plurality of second substrate layers. The first substrate layer is doped with...
|
|
WO/2024/014401A1 |
Provided is a semiconductor device comprising: a semiconductor substrate; an interlayer insulation film that has a contact hole and is provided above the semiconductor substrate; a first alloy layer that is provided below the contact hol...
|
|
WO/2024/012342A1 |
Embodiments of the present application provide a chip and a preparation method. The chip comprises: a substrate, wherein a first through hole penetrating through the substrate from the upper surface to the lower surface is formed in the ...
|
|
WO/2024/013602A1 |
Provided is a transistor of minute size. Said transistor has a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulat...
|
|
WO/2024/012455A1 |
Provided in the present invention are an insulated gate bipolar transistor and a preparation method therefor. The preparation method for an insulated gate bipolar transistor comprises the following steps: providing a semiconductor layer,...
|
|
WO/2024/015668A2 |
In a general aspect, a diode (100) includes a substrate (102) of a first conductivity type, a semiconductor layer (104) of the first conductivity type disposed on the substrate and including a drift region (120), a shield region (110a) o...
|
|
WO/2024/012437A1 |
The present application relates to a lateral insulated gate bipolar transistor and a preparation method therefor. The lateral insulated gate bipolar transistor comprises a drift region (120), a first well region (171), a first electrode ...
|
|
WO/2024/014068A1 |
Provided are: a palladium cobalt oxide thin film; a delafossite-type oxide thin film; a schottky electrode having a delafossite-type oxide thin film; a method for producing a palladium cobalt oxide thin film; and a method for producing a...
|
|
WO/2024/013808A1 |
In a CMOS circuit (C) provided in a frame region as a portion of a driving circuit, a second TFT (9i) having a second semiconductor layer (16b) formed of an oxide semiconductor comprises: a first gate electrode (18b) provided on one fron...
|
|
WO/2024/015287A1 |
Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding ma...
|
|
WO/2024/014149A1 |
An electronic component (1) includes: a lower electrode (51); intermediate electrodes (52) disposed on the lower electrode so as to form projections and recesses together with the lower electrode; and an upper electrode (53) having raise...
|
|
WO/2024/011664A1 |
The embodiments of the present disclosure relate to the field of semiconductors, and in particular to a semiconductor structure and a preparation method. The semiconductor structure comprises: a substrate, a gate dielectric layer, a firs...
|
|
WO/2024/013868A1 |
The present invention increases maximum unipolar current density while relaxing the electric field that acts on a body diode when a transistor is in an off state. A semiconductor device according to the present invention comprises a firs...
|
|
WO/2024/014402A1 |
Provided is a method for manufacturing a semiconductor device, the method comprising: a step for forming an interlayer insulating film having a contact hole above a semiconductor substrate; a step for forming an initial metal film contai...
|
|
WO/2024/011610A1 |
A semiconductor device includes a substrate, an insulating layer, and an epitaxial structure. The first substrate layer is doped with p-type dopants. The second substrate layer is doped with n-type dopants and disposed over the first sub...
|
|
WO/2024/007443A1 |
The present application discloses a GaN-based HEMT having multiple threshold voltages, and a preparation method therefor and an application thereof. The HEMT structure comprises a channel layer and a barrier layer, wherein a two-dimensio...
|
|
WO/2024/008015A1 |
Provided in the present disclosure is an insulated gate bipolar transistor. The transistor comprises: an epitaxial layer; a drift region formed in the epitaxial layer, the drift region having a first doping type; a plurality of super jun...
|
|
WO/2024/010637A1 |
Disclosed herein are compositions comprising gallium oxide doped with carbon, and methods of making and use thereof. In some examples, the methods comprise contacting a first precursor and a second precursor at a first temperature, where...
|
|
WO/2024/009590A1 |
A semiconductor device according to the present invention comprises: a chip which has a first main surface and a second main surface that is on the reverse side of the first main surface; an active region which is provided in the chip; a...
|
|
WO/2024/007386A1 |
Provided in the present application are an array substrate and a display panel. The array substrate comprises a base and a thin film transistor arranged on one side of the base. The capability of the thin film transistor to sense externa...
|
|
WO/2024/007367A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a manufacturing method for a semiconductor structure, and semiconductor structures. A semiconductor structure comprises a window area, a transi...
|
