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WO/2024/052689A1 |
A charged particle trap is disclosed. The charged particle trap comprises a substrate (31) and a layer structure (33, 37, 39) disposed on the substrate, the layer structure including an antenna layer (33) and an electrode layer (39). The...
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WO/2024/051323A1 |
Provided in the present application are a display panel and an electronic terminal. The display panel comprises a substrate and a first thin-film transistor located on the substrate, wherein the first thin-film transistor comprises a fir...
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WO/2024/054463A1 |
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. The methods include treating a surface of a metal gate stack with a radical treatment. The radical treatment may be used to treat one...
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WO/2024/055049A2 |
Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes ar...
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WO/2024/050866A1 |
A gallium oxide device preparation method based on high-temperature annealing technology, and a gallium oxide device. The method comprises: preparing a barrier layer on the surface of a gallium oxide wafer, the barrier layer having a fun...
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WO/2024/053267A1 |
This semiconductor device (10) is provided with: a semiconductor layer (12); a cell trench (14) which is formed in the shape of a mesh in the semiconductor layer (12), while comprising a plurality of first trenches (24) that extend in a ...
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WO/2024/052773A1 |
The present invention provides a transistor which enables the achievement of miniaturization. The present invention also provides a transistor which has good electrical characteristics. This semiconductor device comprises first to third ...
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WO/2024/052952A1 |
A semiconductor device according to the present disclosure comprises: a drift layer including a first pillar region of a first conduction type alternating with a second pillar region of a second conduction type; a base region of the seco...
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WO/2024/054712A1 |
In certain aspects, a chip includes first source/drain contacts formed over a first oxide diffusion (OD), and first gates, wherein each of the first gates is disposed between a respective pair of the first source/drain contacts. The chip...
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WO/2024/053486A1 |
This semiconductor device comprises: a chip having a first main surface on one side and a second main surface on the other side; a first terminal that is disposed on the first main surface; a second terminal that is disposed on the secon...
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WO/2024/053039A1 |
The dynamic resonant frequency changing method has problems with phase tracking, and there is a concern that single-qubit gate errors may occur. The solution is a qubit control method that controls the spin state of qubits formed by char...
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WO/2024/052774A1 |
The present invention provides a semiconductor device which enables the achievement of miniaturization or high integration. According to the present invention, a second layer, a mask and a first resist mask are sequentially formed on a f...
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WO/2024/053457A1 |
Provided is a semiconductor device comprising: a gate electrode layer embedded in a gate trench; a contact trench including a first intersecting region intersecting the gate trench; and an emitter contact electrode layer embedded in the ...
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WO/2024/050951A1 |
The present disclosure relates to a semiconductor structure and a method for forming same. The method for forming the semiconductor structure comprises the following steps: providing an initial substrate; etching the initial substrate to...
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WO/2024/053456A1 |
Provided is a semiconductor device including: a gate electrode embedded in a gate trench; a surface insulating layer that is formed on a first principal surface and that has a contact hole; a covering insulating layer that covers the gat...
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WO/2024/051166A1 |
The present application provides a semiconductor device and a fabrication method therefor, and relates to the technical field of semiconductors. The method comprises: first providing a wide-band-gap substrate; then forming a wide-band-ga...
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WO/2024/052777A1 |
A semiconductor device, such as an integrated circuit, microprocessor, wafer, or the like, includes a first gate all around field effect transistor (GAA FET) (303) and second GAA FET (313, 323, 333) within the same region type (e.g., p-t...
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WO/2024/051061A1 |
The present disclosure relates to a semiconductor structure and a forming method therefor. The forming method for the semiconductor structure comprises the following steps: providing an initial substrate; etching the initial substrate to...
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WO/2024/053485A1 |
This semiconductor device includes: a chip having a main surface; an output region provided on the main surface; a protective region provided on the main surface; an output transistor having a plurality of first trench gate structures fo...
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WO/2024/051493A1 |
The present application relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate; an epitaxial layer located on a surface o...
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WO/2024/051635A1 |
The present invention relates to an HEMT device, comprising: a two-dimensional electron gas structure and at least one pair of dual gates, wherein a two-dimensional electron gas channel is formed in the two-dimensional electron gas struc...
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WO/2024/052772A1 |
The present invention provides a semiconductor device with stable operation. This semiconductor device has a first transistor, a second transistor, a third transistor, and a first capacitance element. One among the source and drain of th...
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WO/2024/053239A1 |
[Problem] The present invention addresses the problem of providing a semiconductor-type quantum bit device having reduced variations in characteristics of quantum bit operations when multiple units thereof are integrated. [Solution] A se...
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WO/2024/052749A1 |
A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside ...
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WO/2024/052643A1 |
A lateral silicon carbide power semiconductor device (31; 101; 141; 161; 181) is disclosed. The device comprises a substrate (102) and a silicon carbide semiconductor structure (105) disposed on the substrate and having a principal surfa...
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WO/2024/052787A1 |
Provided is a semiconductor device having a novel configuration. This semiconductor device has: a first element layer on which a readout circuit is provided; a second element layer on which an amplification circuit is provided; and a thi...
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WO/2024/054763A1 |
In an example, a semiconductor device (10) includes an active trench region (22A) and an intersecting trench region (22C, 22CA, 22CB). The active trench region (22A) includes an active shield electrode (21A) and the intersecting trench r...
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WO/2024/050867A1 |
Provided in the present invention is a preparation method for a silicon carbide (SiC) heterojunction normally-closed high-electron-mobility transistor. The method comprises: selecting an unintentionally doped n-type 4H-SiC wafer as a sub...
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WO/2024/047965A1 |
[Problem] To mitigate an electric field generated in a drift layer when a reverse voltage is applied to a Schottky barrier diode that uses a gallium oxide. [Solution] A Schottky barrier diode 1 comprises: a drift layer 30 and a semicondu...
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WO/2024/046544A1 |
A solid state switch, comprising a first metal–oxide–semiconductor field-effect transistor (MOSFET) comprising: a drain terminal, a source terminal, and a gate terminal. The MOSFET is configured to be switched between an on-state and...
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WO/2024/047784A1 |
A first semiconductor layer (102) is formed on a substrate (101) by crystal growth of a first nitride semiconductor in the direction of the c-axis. A second semiconductor layer (103) made of a second nitride semiconductor having a band g...
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WO/2024/045850A1 |
The present application provides a semiconductor device. A first active layer is located above a substrate; a first insulating layer covers the first active layer, and a first via hole is provided in the first insulating layer; a second ...
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WO/2024/046713A1 |
A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery netw...
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WO/2024/047783A1 |
A high electron mobility transistor according to an embodiment of the present disclosure comprises a heterojunction structure that includes a GaN channel layer in which two recesses are formed with a predetermined gap therebetween. The h...
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WO/2024/045467A1 |
The present disclosure relates to the field of semiconductors, and provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing a semiconductor structure comprises: forming a f...
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WO/2024/048767A1 |
[Problem] To provide a crystal having excellent crystallinity and a laminate structure, and an element, an electronic device, an electronic apparatus, and a system using same. [Solution] Provided is a laminate structure in which an epita...
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WO/2024/044910A1 |
A photosensitive ring oscillator, its preparation method, and a flexible artificial retina. The photosensitive ring oscillators (PROs) based on 2D semiconducting materials have been fabricated on flexible biological compatible substrates...
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WO/2024/045259A1 |
A semiconductor structure and a manufacturing method therefor, the semiconductor structure comprising: a substrate (1) and a word line structure (3). The word line structure (3) comprises: a work function laminated structure (33) located...
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WO/2024/045861A1 |
Embodiments of the present application provide a chip and a manufacturing method therefor, and an electronic device. The problem that a gate control capability of a chip decreases along with miniaturization of a device size is solved. Th...
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WO/2024/048393A1 |
This multilayer structure comprises an amorphous substrate that has an insulating surface, an alignment layer that is arranged on the amorphous substrate, and a semiconductor pattern that contains gallium nitride and is arranged on the a...
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WO/2024/048266A1 |
This semiconductor device comprises: a substrate; a channel layer that is provided on one surface side of the substrate, and that contains a first nitride semiconductor having a first band gap; a barrier layer that is provided on the sub...
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WO/2024/049625A1 |
A method for forming a semiconductor device is disclosed. The method includes forming a first layer on a substrate. The method includes forming a second layer on the first layer. The substrate and the second layer have a first semiconduc...
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WO/2024/047119A1 |
The invention relates to a method for producing a semiconductor component, having the following steps: providing a layer structure of the semiconductor component, wherein the layer structure has a first layer, and the first layer has a I...
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WO/2024/045261A1 |
The present disclosure relates to a semiconductor structure and a preparation method therefor. The semiconductor structure comprises: a substrate (1), and a gate trench (31) located in the substrate (1); and a gate dielectric layer, whic...
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WO/2024/048394A1 |
The present invention includes: an amorphous substrate having an insulating surface; an alignment pattern formed on the amorphous substrate; an insulating layer that is in contact with a side surface of the alignment pattern and that sur...
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WO/2024/044880A1 |
The present application relates to the technical field of display, and discloses a thin film transistor unit and a manufacturing method, and a shift register unit. The thin film transistor unit comprises a first gate, a first gate insula...
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WO/2024/047479A1 |
An electronic device (11) includes a substrate (55), first and second semiconductor devices (22, 33), and a power supply structure (88b). The first semiconductor device (22) includes a first plurality of gate all-around (GAA) field effec...
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WO/2024/048083A1 |
The present invention increases the degree of integration of a semiconductor device. This semiconductor device comprises: a three-dimensional material layer; a first transistor including the three-dimensional material layer; a two-dimens...
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WO/2024/047995A1 |
This semiconductor device comprises: an amorphous substrate having an insulating surface; an orientation pattern located on the amorphous substrate; and a semiconductor pattern including gallium nitride and located on the upper surface o...
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WO/2024/047487A1 |
Provided is a storage device which can be micro-fabricated or highly integrated. The storage device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor element and a transistor on the c...
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