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WO/2024/036826A1 |
Embodiments of the present application provide a vertical transistor, a storage unit and a manufacturing method therefor. In the vertical transistor provided by the embodiments of the present application, a semiconductor layer is configu...
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WO/2024/039417A1 |
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers t...
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WO/2024/037259A1 |
A laterally diffused metal oxide semiconductor device and a preparation method therefor. The laterally diffused metal oxide semiconductor device (1) comprises: a substrate (10), which is provided with a trench (16); a drift region (30), ...
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WO/2024/036486A1 |
A semiconductor device includes a first III-V nitride-based layer, a second III-V nitride-based layer, a nitride-based transition layer, and a nitride-based transistor. The first III-V nitride-based layer is disposed over a substrate by ...
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WO/2024/039416A1 |
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to...
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WO/2024/037906A1 |
The invention relates to a semiconductor device comprising a semiconductor switching element, a semiconductor device package for encapsulating the semiconductor switching element, a first electrode for providing a first voltage to the se...
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WO/2024/038685A1 |
This semiconductor device comprises: a multi-gate transistor in which a plurality of field effect transistors each having a pair of main electrodes and gate electrode arranged between the pair of main electrodes are electrically connecte...
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WO/2024/036747A1 |
The present disclosure relates to a semiconductor structure and a method for forming same. The method for forming the semiconductor structure comprises the following steps: forming a substrate, and a plurality of active regions which are...
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WO/2024/036762A1 |
The present application provides a thin film transistor of a vertical structure and an electronic device. According to the thin film transistor of the vertical structure, a second doped portion is arranged in a via hole of an insulating ...
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WO/2024/037186A1 |
Provided in the present application is an electronic device, comprising a reverse conducting IGBT power device. Further provided in the present application is a preparation method for a reverse conducting IGBT power device. The reverse c...
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WO/2024/038504A1 |
This silicon carbide semiconductor device has, on the upper surface of a semiconductor layer (20), a trench (6) that passes through a source region (3) and a body region (5) and reaches a drift layer (2). On the bottom portion in the tre...
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WO/2024/036665A1 |
The present disclosure relates to the technical field of semiconductors, and relates to a semiconductor structure and a forming method therefor, and a memory. The semiconductor structure of the present disclosure comprises a substrate, a...
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WO/2024/039432A1 |
A semiconductor device having one or more bifacial semiconductor wafers. The bifacial semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar ...
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WO/2024/036895A1 |
A display panel (100) and an electronic terminal. The display panel comprises a substrate (10), an active layer (20) located on the substrate (10), a first electrically conductive layer (30) located on the side of the active layer (20) c...
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WO/2023/231745A9 |
A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. The semiconduc...
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WO/2024/037347A1 |
A semiconductor structure and a method for forming same, wherein the method for forming the semiconductor structure comprises: forming on a semiconductor substrate (200) linear semiconductor patterns (203) extending in a first direction ...
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WO/2024/036792A1 |
The present disclosure relates to the field of power semiconductors, and particularly discloses a super-junction semiconductor device and a manufacturing method therefor. The manufacturing method comprises: etching a first predetermined ...
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WO/2024/039647A1 |
Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and...
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WO/2024/039968A2 |
A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer and a barrier layer and source and drain contacts on the semiconductor layer structure. A gate contact and a multi-layer passivat...
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WO/2024/036518A1 |
The present disclosure belongs to the technical field of radio frequencies. Provided are a radio-frequency switch unit and a preparation method therefor, and an electronic device. The radio-frequency switch unit in the present disclosure...
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WO/2024/037525A1 |
A ferroelectric random-access memory (FeRAM) cell (10) is provided. The FeRAM cell (10) includes a vertical channel (310) between a bottom source/drain region and a top source/drain region (630); a gate oxide (320) surrounding the vertic...
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WO/2024/036676A1 |
The present disclosure provides a fin transistor structure and a manufacturing method therefor. The manufacturing method for a fin transistor structure comprises: providing a substrate, wherein a fin-shaped portion extends out of the top...
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WO/2024/040019A1 |
Semiconductor structures and methods of fabricating semiconductor structures using sublimation are described. An example method includes forming an opening through a mask layer over a wafer. The wafer includes a substrate, a channel laye...
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WO/2024/036716A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure and a forming method therefor. The method comprises: providing a substrate, wherein the substrate comprises a laminated structure and a first isolation s...
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WO/2024/037276A1 |
The present invention relates to the field of semiconductor device manufacturing. Disclosed are an IGBT device having a deep buffer layer and high-density trenches, and a preparation method for the IGBT device. The preparation method com...
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WO/2024/037135A1 |
Disclosed are a semiconductor structure and a manufacturing method. The semiconductor structure comprises: a substrate; active pillars, the active pillars being positioned on the substrate and arranged in an array along a first direction...
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WO/2023/018893A9 |
The disclosure is directed to systems, devices, and methods for generating, stabilizing, and controlling mesoscopic spin order of electrons. The device includes a two-dimensional (2D) semiconductor monolayer configured to accommodate a 2...
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WO/2024/036513A1 |
Provided in one aspect of the present disclosure are a floating-gate memory and a preparation method therefor. The floating-gate memory comprises: a gate layer, on which an insulating layer, a floating-gate layer, a barrier layer and cha...
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WO/2024/037274A1 |
Disclosed are an IGBT device having reverse conduction characteristics and a preparation method therefor, relating to the field of semiconductor device manufacturing. The preparation method comprises the following steps: A, preparing an ...
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WO/2024/038681A1 |
According to the present invention, a front surface side of a semiconductor substrate (30) is provided with a source trench structure that comprises a gate trench (7), in which a gate electrode (9) is buried, and a source trench (11), in...
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WO/2024/033049A1 |
A semiconductor structure according to the invention includes a first source region and a first drain region forming a first L-shaped layout, and a second source region and a second drain region forming a second L-shaped layout, the firs...
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WO/2024/034301A1 |
The present invention provides: a phenanthroline compound from which it is possible to obtain excellent electron injection ability and electron transportation ability when used in an electron injection layer of an organic electroluminesc...
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WO/2024/034023A1 |
In relation to production steps for a device having a structure in which a gate is insulated and separated from a Si substrate in a three-dimensional structure of a GAA-type FET or the like having a laminated channel in which fine line-s...
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WO/2024/033739A1 |
The present invention provides a semiconductor device which comprises a transistor of a very small size. This comprises a first and a second transistor. The first transistor has first to third electrically conductive layers, an insulatio...
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WO/2024/031755A1 |
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a fabrication method therefor. The structure comprises a substrate and a transistor located on the substrate. A first ...
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WO/2024/035857A1 |
A microelectronic device (100) includes a GaN FET (102) on a substrate (104) such as silicon and a buffer layer (106) of p-type GaN semiconductor material. The GaN FET (102) includes a gate electrode extension (146) including p-type GaN ...
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WO/2024/035608A1 |
Group III oxide semiconducting devices with effective device isolation and edge termination regions.
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WO/2024/035473A1 |
Disclosed is a complementary field effect transistor (CFET) formed from stacked 2D-material transistors. The 2D-material transistors are formed from transition metal dichalcogenide (TMD), which are atomically thin semiconductors. The sta...
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WO/2024/033737A1 |
Provided is a low-cost touch panel. This touch panel comprises a transistor, a detection element, an interlayer insulation layer, a connection electrode, and conductive particles, and the detection element has a pair of electrodes. The i...
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WO/2024/034267A1 |
This silicon carbide substrate has a main surface. The main surface is composed of an outer peripheral portion within 3 mm from the outer periphery of the main surface, and a central portion surrounded by the outer peripheral portion. In...
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WO/2024/031756A1 |
The present application provides a thin-film transistor and an electronic component. The thin-film transistor comprises: a crystalline active pattern, comprising: a channel, two contact portions connected to two opposite sides of the cha...
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WO/2024/034433A1 |
The present invention provides a method for producing a silicon substrate for quantum computers, the method comprising: a step for forming an Si epitaxial layer on a silicon substrate by performing epitaxial growth using, as a silicon-ba...
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WO/2024/034277A1 |
A unit cell (16) is a section between the centers of adjacent source trenches (11), includes two or more gate trenches (7) and one source trench (11), and has four or more channels formed therein. The two or more gate trenches (7) and th...
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WO/2024/034411A1 |
The present disclosure relates to: a semiconductor device which makes it possible to achieve both the suppression of a short channel effect and an increase in driving capability; and a method for manufacturing same. The semiconductor dev...
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WO/2024/032337A1 |
Provided in the embodiments of the present application are an LDMOS device. The LDMOS device comprises: an N-type substrate; a source region and a drain region, wherein the source region and the drain region are arranged in the lengthwis...
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WO/2024/035502A1 |
An etch and surface modification is performed in a plasma, in which ions have been removed so that radicals of the plasma form a modified surface of a layer of substrate. A gas chemistry is reacted with the modified surface to form a rea...
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WO/2024/033735A1 |
The present invention provides a semiconductor device which achieves both low power consumption and high performance. This semiconductor device comprises first and second transistors, and a first insulating layer. The first transistor co...
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WO/2024/032108A1 |
Embodiments of the present disclosure provide a semiconductor structure, a preparation method for a semiconductor structure, and a semiconductor memory. The semiconductor structure comprises: a channel doped region; a drain doped region ...
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WO/2024/034926A1 |
The present invention relates to an atomic layer deposition (ALD) method for forming an IGZO channel layer of a transistor device, the method comprising: a deposition cycle step of performing a deposition cycle for depositing an IGZO cha...
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WO/2024/034007A1 |
In a first step S101, a first region having a polarity inversion layer and a second region having no polarity inversion layer are disposed on a substrate. Next, in a second step S102, on the substrate having the first and second regions,...
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