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WO/2024/009712A1 |
Provided is a pressure sensor device that can reduce the arrival of liquid at a detection part. This pressure sensor device comprises a base substrate, a detection element that is mounted on an upper surface of the base substrate and has...
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WO/2024/007385A1 |
The present application provides a semiconductor device and an electronic apparatus. The semiconductor device comprises a metal layer arranged on the side of an active layer facing a buffer layer, the metal layer comprises at least one m...
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WO/2024/009591A1 |
This semiconductor device includes: a chip having a first main surface and a second main surface on the opposite side; an active region provided on the chip; an element structure formed in the active region on the first main surface; and...
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WO/2024/007990A1 |
A shorted-anode lateral insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises: a drift region (103) having a first conductivity type; a collector region (109) provided in the drift region (103) a...
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WO/2024/009096A1 |
A system for quantum information processing (1) is described which includes a body of material (2) having first and second opposite faces (3, 4) and at least one two- dimensional array (7) of defects (5i,k, 5i+1,k, 5i,k+1... 5n,m) embedd...
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WO/2024/007742A1 |
The present invention provides vertically stacked lateral gate-all-around metal-oxide-semiconductor field-effect transistors (referred to as lateral gate-all-around transistors), a structure of a novel three-dimensional integrated circui...
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WO/2024/009047A1 |
The invention relates to a quantum device (100) with semiconductor qubits, comprising at least:• - a layer (104) of a first semiconductor arranged on a layer (106) of a second semiconductor, the forbidden energy band of which is differ...
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WO/2024/009094A1 |
The device includes a body of material, at least one conduction path running through the body of material and formed by irradiation of a region of the material defining the at least one conduction path. The at least one conduction path i...
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WO/2024/007394A1 |
A semiconductor structure (10), a memory and an operation method thereof. The semiconductor structure (10) comprises: a substrate (100); a first gate structure (110) and a second gate structure (120) which are located on a surface of the...
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WO/2024/004350A1 |
This MEMS accelerometer comprises a substrate on which a first beam and movable second beam, and a third beam and movable fourth beam are provided. The first, second, third, and fourth beams are separated by isolation portions into first...
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WO/2024/001197A1 |
The present application relates to a shorted-anode lateral insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a drift region, a collector region arranged in the drift region, an anode region, ...
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WO/2024/004079A1 |
The present invention addresses the problem of suppressing variation in device properties that are caused by a buried gate electrode. This nitride semiconductor device comprises a substrate, a first nitride semiconductor layer, a second ...
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WO/2024/005152A1 |
Provided is a technique with which it is possible to increase the breakdown voltage characteristics of a semiconductor region that includes a crystalline oxide semiconductor that includes gallium, or a semiconductor device that has a sem...
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WO/2024/001276A1 |
A preparation method for a Si-based GaN-HEMT device, relating to the technical field of semiconductors. The method comprises the following steps: S100, preparing a U-shaped groove on an epitaxial wafer; S200, sequentially preparing P-typ...
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WO/2024/001693A1 |
Provided are a device, a module, and an apparatus, which have good reliability and long service life. The device can comprise a first semiconductor layer provided on a substrate, a second semiconductor layer epitaxially formed on the fir...
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WO/2024/002792A1 |
A quantum device comprising an array of quantum dots is disclosed. The quantum device comprises a silicon layer in which quantum dots (201) can be induced by respective gates; gates of the inducible quantum dots (201) for controlling an ...
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WO/2024/005789A1 |
IC devices with logic circuits using vertical transistors with backside source or drain (S/D) regions, and related assemblies and methods, are disclosed herein. An example vertical transistor includes an elongated structure (e.g., a nano...
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WO/2024/005870A1 |
Silicon germanium (SiGe)Zsilicon containing superlattice structure and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of german...
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WO/2024/001422A1 |
The present invention relates to the technical field of power semiconductor devices, and in particular to a trench silicon carbide MOSFET integrated with a high-speed freewheeling diode and a preparation method therefor. The MOSFET of th...
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WO/2024/000431A1 |
The present disclosure relates to a semiconductor device, comprising: a barrier layer; a channel layer, which is adjacent to the barrier layer, wherein a two-dimensional carrier gas is formed at the position in the channel layer close to...
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WO/2024/001468A1 |
Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) stacked above a second FET in a non-step nanosheet structure, and a bottom contact electrically connected to a first bottom source...
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WO/2024/000433A1 |
The present invention relates to a diode, comprising: a first barrier layer; a second barrier layer; a channel layer located between the first barrier layer and the second barrier layer and comprising a first portion and a second portion...
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WO/2024/004016A1 |
A semiconductor device (90) comprises, in this order: first to third channel layers (41-43) comprising group III-V semiconductors containing Fe and C; and a barrier layer (50) comprising a group III-V semiconductor having a bandgap wider...
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WO/2024/006912A1 |
A field effect transistor including a substrate having an upper surface thereof. An epitaxial layer including n-type is material disposed over the upper surface of the substrate. A P-well including P-type material is diffused within an u...
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WO/2024/000494A1 |
A display substrate, a preparation method therefor, and a display apparatus. The display substrate comprises: a substrate (101), and at least one transistor (100) provided on the substrate (101). The transistor (100) comprises: an active...
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WO/2024/003212A1 |
A semiconductor array structure includes a substrate; a plurality of field effect transistors (FETs) arranged in rows and located on the substrate, each comprising a first source-drain region, a second source-drain region, at least one c...
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WO/2024/001689A1 |
The present application relates to the technical field of semiconductors. Provided are a chip and a manufacturing method therefor, and an electronic device, by means of which the manufacturing process of a chip can be simplified. The chi...
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WO/2024/004431A1 |
The present invention improves yield. This semiconductor device comprises: a volumetric-shaped semiconductor portion that has an upper surface portion, a lower surface portion, and a side surface portion; an underlayer film which is prov...
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WO/2024/002009A1 |
The present disclosure relates to a multi-gate hybrid-channel field effect transistor (FET) structure (100). The FET structure (100) may be used to fabricate an integrated device like a nanosheet device or forksheet device. The FET struc...
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WO/2024/005015A1 |
The present invention comprises: a voltage generation unit that has a vibration body 22a1 and a fixed electric potential electrode 24 in contact with a reception surface of the vibration body 22a1, and that generates voltage on the outpu...
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WO/2024/005806A1 |
Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an "angled transistor" if a longitudinal axis of an elongated semiconductor structure...
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WO/2024/003523A1 |
There is provided a logic gate comprising a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge accepting layer and a second charge accepting layer. The first charge accepting ...
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WO/2024/006921A1 |
A gate driver circuit which integrates a synchronous bootstrap circuit in an isolation well of an integrated circuit, such that the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding ...
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WO/2024/001801A1 |
Some embodiments of the present application relate to the technical field of semiconductors, provide an integrated circuit and a preparation method therefor and an electronic device, and aim to improve the yield of devices in the integra...
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WO/2024/001327A1 |
A MOSFET device and a manufacturing method therefor. The manufacturing method comprises: first, implanting first ions by using a patterned mask layer (200), so as to form a well region (101), which is not prone to diffusion; then, implan...
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WO/2024/004126A1 |
This domain wall displacement element comprises a first magnetoresistance effect element and a first transistor. A first domain displacement layer of the first domain displacement layer is electrically connected to the first active regio...
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WO/2024/005153A1 |
The present invention provides a technology which is capable of enhancing the withstand voltage of a semiconductor device that comprises a semiconductor region or semiconductor layer which contains a crystalline oxide semiconductor conta...
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WO/2024/000183A1 |
A nitride-based semiconductor device includes a first nitride-based transistor, a second nitride-based transistor, and a first electrical compensation layer. The first nitride-based transistor includes a first gate electrode and a first ...
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WO/2024/000631A1 |
The present application provides a thin film transistor and a manufacturing method therefor, and a display panel. The thin film transistor at least comprises a first gate, a first insulating layer, an active layer, a source and a drain, ...
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WO/2024/001335A1 |
A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at...
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WO/2024/000432A1 |
The present invention relates to a semiconductor device, comprising: a channel layer comprising a first portion and a second portion, the first portion comprising a first region, a second region and a third region, the second region bein...
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WO/2024/004683A1 |
An emitter electrode of a semiconductor device (40) has an Al electrode (422) and a Ni electrode (423) disposed on the Al electrode (422). A solder (91) that joins the emitter electrode and a conductive spacer (70) contains Cu and Sn. An...
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WO/2024/005610A1 |
The present invention relates to a thin film transistor and a method for manufacturing a thin film transistor. The method for manufacturing a thin film transistor, according to an embodiment, may comprise the steps of: forming a diffusio...
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WO/2024/001779A1 |
Disclosed in the present application is a super junction power device. The super junction power device comprises a first semiconductor layer and a second semiconductor layer, which are arranged in a stacked manner, wherein the first semi...
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WO/2023/248670A1 |
The description of the present application discloses a technology for enhancing the reliability of a semiconductor device. A semiconductor device according to the technology disclosed in the description of the present application is prov...
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WO/2023/245712A1 |
Embodiments of the present invention relate to the technical field of semiconductors, and provide a semiconductor structure and a manufacturing method therefor, for use in solving the technical problem that the semiconductor structure ha...
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WO/2023/248530A1 |
An MEMS acoustic element (101) comprises: a first substrate (51) having a first through-hole (51e); a second substrate (52) that is disposed so as to block the first through-hole (51e) and at least partially overlap the first substrate (...
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WO/2023/245539A1 |
Provided in the present disclosure are a display substrate, a display panel, and a display apparatus. The display substrate comprises a base substrate, which comprises a display region and a frame region, which is located on at least one...
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WO/2023/249625A1 |
IC devices with angled transistors and angled routing tracks, and related assemblies and methods, are disclosed herein. A transistor is referred to as an "angled transistor" if a longitudinal axis of an elongated semiconductor structure ...
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WO/2023/249846A2 |
Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.
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