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WO/2024/064326A1 |
Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The transistor device includes a gate contact having a g...
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WO/2024/062664A1 |
Provided is a semiconductor device which has, during an OFF time, a carrier discharge path that is provided in an IGBT, and increases an IE effect while assuring breakdown resistance against avalanches, and is thereby capable of reducing...
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WO/2024/062829A1 |
In the present invention, a transistor comprises a collector layer, a base layer, and an emitter layer stacked in this order on an upper surface, which is one surface of a substrate. Four or more emitter electrodes are electrically conne...
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WO/2024/060262A1 |
The present application discloses a semiconductor device, a manufacturing method, a power conversion circuit, and a vehicle. The semiconductor device comprises: an N-type semiconductor substrate, a first epitaxial layer, multiple gate tr...
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WO/2024/060366A1 |
Provided in the present application is a display panel. The display panel comprises a substrate, and a first ohmic contact structure, a first boss, a second ohmic contact structure, a semiconductor structure and a gate, which are stacked...
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WO/2024/060646A1 |
A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first...
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WO/2024/060514A1 |
A display panel (100). The display panel (100) comprises a substrate (11) and a thin film transistor (101) provided on the substrate (11). The thin film transistor (101) comprises: a first gate (14), comprising a first inclined side surf...
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WO/2024/060220A1 |
A nitride-based semiconductor device includes a nitride-based semiconductor structure, a doped nitride-based semiconductor layer, and a gate electrode. The nitride-based semiconductor structure has an active region and an isolation regio...
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WO/2024/064797A1 |
Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a source/drain (120) substantially enclosed in a source/drain silicide layer (124), wherein an integral source/drain via port...
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WO/2024/064567A2 |
In an aspect, a transistor comprises a gate structure having a metal gate, a dielectric layer at least partially surrounding the metal gate, a metal cap over a portion of the metal gate that is not surrounded by the dielectric layer, and...
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WO/2024/063588A1 |
The present invention relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device, according to an embodiment, may comprise the steps of: forming a thin film structure on a substrate;...
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WO/2024/063744A2 |
The present invention relates to a method (100) for enabling the use of an liquid-air interface in order to create the colloidal quantum well film desired to be created on a substrate surface.
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WO/2024/055667A1 |
The present application provides a capacitor structure, a capacitor array, a memory, and an electronic device. The capacitor structure comprises at least one field effect transistor having connected first and second electrodes. The field...
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WO/2024/056193A1 |
A method for manufacturing a SiC semiconductor element (10), comprising the steps of providing a SiC substrate (20) with a SiC epitaxial layer (30) on top, treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PII...
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WO/2024/055885A1 |
Provided in the present application are a semiconductor device and a preparation method therefor, which realize ohmic contact between a first electrode layer and an epitaxial layer, reduce the contact resistivity of ohmic contact, are co...
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WO/2024/058355A1 |
The present invention relates to: a semiconductor device having, as a gate dielectric layer, an amorphous fluorinated carbon thin film that has a high dielectric constant, low leakage current, and high insulation strength and is thus use...
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WO/2024/058824A1 |
A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor struct...
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WO/2024/055422A1 |
The present disclosure relates to a semiconductor structure and a forming method thereof, and an operation method of the semiconductor structure. The semiconductor structure comprises: a substrate; a storage array comprising a plurality ...
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WO/2024/055294A1 |
The present disclosure provides a semiconductor device and a method of manufacturing the same. In some embodiments, the semiconductor device includes: a substrate; a first nitride semiconductor layer on the substrate; a second nitride se...
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WO/2024/055371A1 |
Disclosed in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises: a substrate; a stacked structure, located on the substrate and...
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WO/2024/058180A1 |
The present invention relates to a substrate (1) which is for forming a semiconductor device, and has: a diamond substrate (10); and a silicon carbide layer (20) disposed on a portion or the entirety of one surface (10a) of the diamond s...
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WO/2024/057165A1 |
Provided is a storage device which can be micro-fabricated or highly integrated. This storage device has a plurality of memory cells, a first insulator, and a second insulator disposed on the first insulator. Each of the memory cells has...
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WO/2024/058140A1 |
This semiconductor device is provided with: a semiconductor substrate (10) which has a main surface (10a); a drift layer (31) of a first conductivity type, the drift layer being formed in a main surface (10a)-side surficial part; a drain...
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WO/2024/056344A1 |
A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stac...
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WO/2024/056345A1 |
A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region (28) located on each side of a function...
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WO/2024/057654A1 |
The present invention provides a semiconductor device with a vertical, the vertical element having drift region of a first conductivity type provided on a semiconductor substrate, a first injection portion provided below the drift region...
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WO/2024/055613A1 |
Disclosed is a novel-topology HEMT device, comprising: a substrate, a semiconductor layer, and a plurality of basic units. In a direction perpendicular to the plane where the substrate is located, an orthographic projection of the shorte...
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WO/2024/057168A1 |
The present invention provides a semiconductor device which achieves both low power consumption and high performance. This semiconductor device comprises a first conductive layer, a second conductive layer, a first semiconductor layer, a...
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WO/2024/039853A9 |
In some embodiments, an integrated circuit includes multiple charge storage regions configured to receive charge carriers from a photodetection region in response to a single excitation of a sample. In some embodiments, an integrated cir...
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WO/2024/057671A1 |
Provided are: a sputtering target for oxide semiconductor thin film formation with which can be formed an oxide semiconductor thin film suitable for an active layer with both high mobility and a high band gap; a method for producing the ...
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WO/2024/055276A1 |
The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, an ohmic electrode, a first field plate, and a second field plate. The second nitrid...
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WO/2024/055902A1 |
The present invention provides a JBS diode structure and a preparation method therefor. The JBS diode structure comprises a first conductive type substrate, a first conductive type epitaxial layer, second conductive type well regions, a ...
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WO/2024/055776A1 |
An HEMT contact hole structure and a preparation method therefor. The HEMT contact hole structure comprises a substrate (11), a buffer layer (12), a channel layer (13), a barrier layer (14), and contact holes (143). The buffer layer (12)...
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WO/2024/057106A1 |
A semiconductor includes a first GAA FET (303) and second GAA FET (305). The second GAA FET includes a first gate dielectric (391) and second gate dielectric (472) within its gate structure. The first GAA FET includes just the first gate...
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WO/2024/057672A1 |
The present invention enables the achievement of: a sputtering target for the formation of an oxide semiconductor thin film, the sputtering target being capable of forming an oxide semiconductor thin film which is suitable for an active ...
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WO/2024/058044A1 |
This silicon carbide epitaxial substrate comprises a silicon carbide substrate and a silicon carbide epitaxial layer. The silicon carbide epitaxial layer is disposed on the silicon carbide substrate. The silicon carbide epitaxial layer h...
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WO/2024/058354A1 |
The present invention relates to a semiconductor structure comprising an amorphous fluorinated carbon ultra-thin film having a high dielectric constant, low leakage current, and high dielectric strength, and a semiconductor device and a ...
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WO/2024/057845A1 |
This silicon carbide substrate has a first main surface, a second main surface, and a basal surface dislocation. The second main surface is positioned on the opposite side from the first main surface. The basal surface dislocation has a ...
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WO/2024/057166A1 |
Provided is a semiconductor device configured to allow miniaturization or an advanced degree of integration. This semiconductor device has a first transistor, a connection part, a first insulator, a second insulator, and first wiring. Th...
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WO/2024/057598A1 |
Provided is a gate drive circuit for a semiconductor switching element, the gate drive circuit driving and controlling the semiconductor switching element by using two independent gate electrodes, and being characterized in that the time...
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WO/2024/056186A1 |
This disclosure relates to a gate all around (GAA) device made based on a GAA transistor structure that comprises a stack of multiple semiconductor channel layers and one or more first gate layers alternatingly arranged along a first dir...
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WO/2024/058046A1 |
A semiconductor quantum device (1) according to the present disclosure comprises: a transistor structure (T) having a source (S), a drain (D), and a gate (G1); one or more quantum dot structures (3-1 to 3-n) where charge localization is ...
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WO/2024/057167A1 |
Provided is a storage device that enables high integration. The storage device comprises a first transistor and a second transistor on the first transistor. The first transistor has a first oxide semiconductor that is on a substrate, a f...
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WO/2024/058144A1 |
This chip sized package-type semiconductor device (1), which is able to be face-up mounted, comprises: a semiconductor layer (40); a vertical MOS transistor (10) which is formed within the semiconductor layer (40); a protective film (35)...
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WO/2024/053396A1 |
Provided is a sensor device that measures an external electric field with high measurement sensitivity.　This sensor device is capable of measuring the electric field intensity of an external electric field. The sensor device comprises:...
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WO/2024/050900A1 |
Disclosed in the present invention is an ASIC chip, which can measure the stress in each direction by a 'four-corner and center' symmetric delay chain combination distributed in three dimensions in the ASIC chip. Further disclosed in the...
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WO/2024/050909A1 |
Embodiments of the present disclosure provide a semiconductor device and a forming method therefor. The semiconductor device comprises: a substrate; and a plurality of storage arrays sequentially stacked on the substrate along a third di...
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WO/2024/050906A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure, a forming method therefor and a layout structure. The semiconductor structure comprises: a substrate, and transistor structures which are located on the...
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WO/2024/052784A1 |
Provided is a display device having a high display quality. This display device has pixels, a scanning line driving circuit, and a power supply circuit. The pixels each have first and second transistors, and the second transistor has a s...
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WO/2024/053022A1 |
A semiconductor device comprises a gate trench (22) formed in an active region (50); a gate insulating film (10) and a gate electrode layer (11) formed inside the gate trench (22); a gate wiring electrode (15) formed on an interlayer ins...
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