Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/090243
Kind Code:
A1
Abstract:
A semiconductor device (1) is provided with, in plan view: a transistor (10) formed in a first region (A1) of a semiconductor layer (40); a transistor (20) formed in a second region (A2) adjacent to the first region (A1) of the semiconductor layer (40); and a drain pad (151) formed in a third region (A3) not overlapping with the first region (A1) or the second region (A2). In plan view, the first region (A1) and the second region (A2) result from bisecting the surface area of a region of the semiconductor layer (40) excluding the third region (A3). In plan view, the transistor (10) and the transistor (20) are lined up in a first direction. The center of the third region (A3) is on a rectilinear center line (90) that bisects the semiconductor layer (40) in the first direction and that is orthogonal to the first direction. In plan view, the drain pad (151) is encompassed by the third region (A3).
Inventors:
ITO YUSUKE
MAEDA TAKAHIRO
KIMURA AKIRA
INOUE TSUBASA
MITSUDA MASAHIRO
MAEDA TAKAHIRO
KIMURA AKIRA
INOUE TSUBASA
MITSUDA MASAHIRO
Application Number:
PCT/JP2023/037194
Publication Date:
May 02, 2024
Filing Date:
October 13, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
H01L29/78
Domestic Patent References:
| WO2019156215A1 | 2019-08-15 |
Foreign References:
| JP2016164962A | 2016-09-08 | |||
| JP2010092895A | 2010-04-22 | |||
| JP2019129312A | 2019-08-01 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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