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WO/2023/241161A1 |
Provided in the present invention are an antiferromagnetic magnetic random access memory device and a manufacturing method therefor. The device comprises a ferromagnetic thin-film structural body, an antiferromagnetic thin-film structura...
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WO/2023/244907A1 |
The disclosed computer-implemented method may include systems and methods for automatically generating sound event subtitles for digital videos. For example, the systems and methods described herein can automatically generate subtitles f...
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WO/2023/242956A1 |
This memory device includes a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in a plan view, and hole groups generated by the impact ionization phenomenon are retained inside a ch...
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WO/2023/244915A1 |
A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions ...
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WO/2023/244986A1 |
A method for providing a shareable media hosting platform includes recording, by a user device, multiple video segments corresponding to a narrative of a user. The method further includes storing, in a memory, the multiple video segments...
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WO/2023/240952A1 |
A data information storage method based on recombinant plasmid DNA molecules. A recombinant plasmid library is composed of universal information storage DNA recombinant plasmids, and the plasmids in the plasmid library record, by using c...
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WO/2023/244272A1 |
A method includes obtaining a video having image frames, and determining, for each respective image frame, a corresponding frame content score based on a visual content thereof. The method also includes selecting, from the image frames, ...
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WO/2023/244583A1 |
A selector for a memory cell in a memory array may operate by opening different conductive paths to high and low voltages during set and reset operations. A first transistor may open a conductive path between a high voltage and a termina...
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WO/2023/242668A1 |
Provided is a novel semiconductor device. In the present invention, a first circuit is electrically connected to a second circuit via a first wire, the first circuit is electrically connected to a fourth circuit via each of a third wire ...
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WO/2023/244361A1 |
A method and system for uploading a media file container from a first device to a second device are described herein, including receiving an instruction to upload the media file container and in response, reading a metadata box of the me...
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WO/2023/244473A1 |
A controller iteratively activates a control signal for one-half a clock cycle while sweeping its phase relationship to the rising edge of the clock. Phase relationships that result in the rising edge of the clock occurring while the con...
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WO/2023/236245A1 |
The present disclosure provides a logic analysis decoding method, comprising the following steps: acquiring a sampling file of a memory circuit block, and generating an instruction sequence file of the memory circuit block, the sampling ...
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WO/2023/239486A1 |
A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shi...
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WO/2023/239556A1 |
In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associate...
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WO/2023/236268A1 |
A bit breakdown condition determining method and device. The method comprises: determining a plurality of first breakdown conditions (S101); breaking down, according to each first breakdown condition, a corresponding first bit respective...
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WO/2023/236269A1 |
Provided in the embodiments of the present disclosure are a phase adjustment circuit, a delay-locked circuit and a memory. The phase adjustment circuit comprises a measurement module, a comparison module, a counting module and an adjustm...
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WO/2023/236528A1 |
The present application discloses a hard disk head and a preparation method therefor, and a hard disk. The top end of a super-lubricity gasket of the hard disk head is fixedly connected to the bottom of a head slider by means of an adhes...
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WO/2023/236258A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided is a memory system. The memory system comprises: a basic chip and a plurality of stacked memory chips, wherein each memory chip comprises a plurali...
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WO/2023/238906A1 |
A fluorine-containing ether compound represented by R1-[B]-[A]-CH2-R2[-CH2-R3-CH2-R2]z-CH2-[C]-[D]-R4 ([A] is formula (2-1). [B] is formula (2-2). [C] is formula (3-1). [D] is formula (3-2). R4 is formula (4). R1 is a terminal group that...
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WO/2023/236996A1 |
The present application relates to the technical field of computers. Disclosed are a memory module and an electronic device. In the memory module, the number of DRAM particles in a rank is increased so as to reduce the number of bits of ...
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WO/2023/236748A1 |
Provided in the embodiments of the present application are a power switch circuit, an electrically programmable fuse memory and an electronic device, which are applied to the technical field of data storage. The electrically programmable...
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WO/2023/236831A1 |
The present invention relates to the technical field of display, and provides a display substrate and a display device. The display substrate comprises a shift register disposed on a base substrate, the shift register comprises a multi-s...
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WO/2023/239301A1 |
The present disclosure describes techniques for voice-controlled content creation. The techniques comprise monitoring voice commands spoken by a creator. Recording of a content may be initiated in response to recognizing a first voice co...
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WO/2023/238698A1 |
A semiconductor device according to an embodiment of the present disclosure comprises: a plurality of fuse elements; and a selection element that is provided in common in the plurality of fuse elements, and switches the plurality of fuse...
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WO/2023/239471A1 |
Memory arrays employing flying bit lines to increase effective bit line length for supporting higher performance, increased memory density, and related methods. To increase memory density, the memory array has a first memory sub-bank and...
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WO/2023/236304A1 |
Disclosed in the present invention are a high-speed large-current adjustable pulse circuit, and an operation circuit and operation method for a phase change memory. The high-speed large-current adjustable pulse circuit is provided with a...
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WO/2023/238487A1 |
A recording medium 100 according to one aspect of the present disclosure comprises a first dielectric layer 20A, a second dielectric layer 20B, and a recording layer 10. The recording layer 10 has a recording region for recording informa...
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WO/2023/231164A1 |
A semiconductor device and a memory. The semiconductor device comprises a pull-up circuit integration area (61), a pull-down circuit integration area (62), and a compensation circuit integration area (63) that do not overlap each other; ...
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WO/2023/232697A1 |
According to an aspect of the present inventive concept there is provided a molecular synthesis array comprising: a substrate; an insulating layer (202) arranged on the substrate; a plurality of column lines (102) extending in parallel a...
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WO/2023/230886A1 |
Provided in the present disclosure are an audio control method and control apparatus, a driving circuit, and a readable storage medium. The audio control method according to some embodiments of the present disclosure is applicable to a d...
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WO/2023/231756A1 |
The present application discloses a three-dimensional stacked chip and a data processing method therefor. The three-dimensional stacked chip comprises a storage die layer and a logic die layer stacked on the storage die layer. The storag...
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WO/2023/232696A1 |
According to an aspect of the present inventive concept there is provided a molecular synthesis array (100, 100') comprising: a substrate (208, 208'); an insulating layer (202, 202') arranged on the substrate (208, 208'); a plurality of ...
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WO/2023/233875A1 |
A cradle 100A which is a contact operation device comprises: an arm 111 having, at the distal end thereof, a contact operation part 114 that contacts a touch panel 205; and a support part 120 supporting the arm 111, said support part 120...
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WO/2023/235216A1 |
A 3D memory device includes a plurality of mats that each include a memory array stacked over logic circuitry supporting operations of the memory array. The logic circuitry include a local column decoder under the memory array for select...
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WO/2023/231166A1 |
Embodiments of the present disclosure provide a fuse circuit, comprising: a fuse unit array, the fuse unit array being operated according to a received first enable signal; and an address signal generation module coupled to the fuse unit...
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WO/2023/235202A1 |
A shared data strobe signal is applied to time data reception simultaneously in two or more transactionally-independent memory channels, lowering strobe signaling overhead by at least half relative to conventional strobe-per-channel solu...
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WO/2023/231263A1 |
Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising: a refresh control circuit, a repetitive command processing circuit and an address generator. The refresh control circuit is used ...
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WO/2023/231295A1 |
A refresh address generation circuit and method, and a memory and an electronic device. The refresh address generation circuit comprises a refresh control circuit (100) and an address generator (200), wherein the refresh control circuit ...
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WO/2023/235115A1 |
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate ind...
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WO/2023/235339A1 |
Systems, devices, and methods for a laser diode assembly (102) including: a laser diode (120) configured to emit a laser beam (200); and a housing (124) configured to receive at least a portion of the laser diode (120), where the housing...
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WO/2023/231177A1 |
The present disclosure provides a receiving circuit and a memory. The receiving circuit comprises: an input buffer, configured to receive a first input signal and a second input signal and compare the first input signal with the second i...
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WO/2023/232749A1 |
A system for the electrochemical synthesis of polymers, comprising: a. one or more reaction chambers comprising an inlet, an outlet, and a plurality of reaction sites comprising one or more individually addressable electrodes, b. a plura...
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WO/2023/231090A1 |
A termination impedance parameter generation method and test system. The method comprises: when a first operation instruction is received, writing a plurality of preset control words into a first data queue in a data buffer (S201), where...
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WO/2023/235157A1 |
A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to a...
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WO/2023/231273A1 |
Provided in the present disclosure are a test method, test equipment and a computer storage medium. The method comprises: determining an initial clock signal; generating a target clock signal on the basis of the initial clock signal; acq...
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WO/2023/231223A1 |
Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising a refresh control circuit and an address generator. The refresh control circuit sequentially receives a plurality of first refresh...
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WO/2023/235037A1 |
The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses with...
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WO/2023/231276A1 |
The present invention relates to the field of very-large-scale integrated circuit testability design. Disclosed is a chiplet test circuit based on flexible configurable modules (FCMs). A circuit core structure is located in an intermedia...
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WO/2023/230835A1 |
A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit (Isc...
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WO/2023/235055A1 |
Computer memory systems employing localized generation of a global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods. The memory system includes one or more memory b...
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