Document |
Document Title |
WO/2023/226112A1 |
Provided in the embodiments of the present disclosure are a refresh control circuit, a memory, and a refresh control method. The refresh control circuit comprises: a processing module which is configured to receive a refresh command sign...
|
WO/2023/226066A1 |
A GOA (Gate Driver On Array) circuit and a display panel. The present invention employs a first GOA unit (sGOA) of each stage of GOA module to realize upward and downward signal transmission, so as to reduce the number of thin film trans...
|
WO/2023/229816A1 |
A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memor...
|
WO/2023/226417A1 |
A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial...
|
WO/2023/225847A1 |
A shift register unit, comprising: a sensing control circuit (1), connected to a sensing signal input end (INPUT2), a random signal input end (OE), and a sensing control node (H), and configured to write a signal provided by the sensing ...
|
WO/2023/229815A1 |
Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets th...
|
WO/2023/229807A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge p...
|
WO/2023/229369A1 |
A video storage apparatus according to an embodiment of the present invention comprises: a spare power source that supplies auxiliary power; a main board that selects, from videos transmitted over a network, a video to store; a video sto...
|
WO/2023/229009A1 |
An aspect of the present disclosure provides a grinding liquid composition that can reduce residue of silica on a substrate surface after grinding is performed, while maintaining a grinding rate. One aspect of the present disclosure pe...
|
WO/2023/225704A1 |
The present invention relates generally to the field of digital content, and more particularly to an improved system and methods for producing, mixing, and recording content. In particular, the system may include a plurality of input cha...
|
WO/2023/226060A1 |
Provided in the present application is a counter circuit, comprising an addition module, a subtraction module and a plurality of control modules. The addition module comprises a plurality of stages of counting modules for corresponding b...
|
WO/2023/229840A1 |
A double data rate (DDR) physical (PHY) provides an interface between a memory controller and a dynamic random-access memory (DRAM). The DDR PHY includes a first set of core logic configured to convert data between a single data rate and...
|
WO/2023/229683A1 |
Techniques are described for managing video editing projects using single bundled video files. A single bundled video file is a new type of file that is in a video container format and that can be used to store and re-create a video edit...
|
WO/2023/227027A1 |
The present disclosure relates to the technical field of display and provides a shift register and a drive circuit and method therefor, a display panel, and a device. The shift register comprises an input unit, a first control unit, an o...
|
WO/2023/229524A1 |
A computing system is provided which includes a client computing device including a processor. The processor is configured to execute a client program to display a first video published by a first user on a video server platform, to a se...
|
WO/2023/225946A1 |
Provided in the embodiments of the present disclosure are a shift register unit, a driving control circuit, a display apparatus and a driving method. The shift register unit comprises: an input circuit, which is configured to provide an ...
|
WO/2023/229808A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corres...
|
WO/2023/226540A1 |
Provided in the present invention are a magnetic random access memory device and a manufacturing method therefor. The device comprises magnetic thin film structure bodies, and an electrode capable of applying voltage to a magnetic thin f...
|
WO/2023/228544A1 |
A compound according to one embodiment of the present disclosure is represented by formula (1). In formula (1), R1 to R4 each independently is an optionally substituted hydrocarbon group.
|
WO/2023/226453A1 |
Disclosed in the present application are a silicon-wafer system and a repair method therefor, and an electronic device. By means of an optical interconnection layer which is additionally provided between a processor layer and a memory la...
|
WO/2023/226062A1 |
Provided in the present application is a counter circuit. The counter circuit comprises multiple stages of counting modules corresponding to binary digits. Each stage of counting module is used for obtaining a carry signal and a present-...
|
WO/2023/226061A1 |
Embodiments of the present disclosure provide an instruction test method and device, a test platform, and a readable storage medium, and relate to the technical field of semiconductors. The method comprises: when a target instruction to ...
|
WO/2023/229814A1 |
A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the...
|
WO/2023/226128A1 |
Disclosed in the embodiments of the present disclosure are a delay adjustment method, a storage chip architecture and a semiconductor memory. The method comprises: measuring a first delay of a first signal path; on the basis of the first...
|
WO/2023/228553A1 |
In the present invention, a reference potential used for detecting data stored in memory cells is optimized in accordance with the positions where the memory cells are arranged. This nonvolatile storage device includes memory cells and r...
|
WO/2023/228869A1 |
The standard for computing storage capacity in modern computing is a bit, and the number of transistors (elements) that are to be nodes, namely, the number of bits is a quantitative unit of modern information communication. In contrast, ...
|
WO/2023/226235A1 |
Provided in the embodiments of the present disclosure are a magnetic random access memory and a read-write method therefor, and a storage apparatus. The magnetic random access memory comprises a storage array, a write circuit and a write...
|
WO/2023/221391A1 |
Embodiments of the present disclosure provide an anti-fuse circuit, comprising: an anti-fuse unit; a programming circuit, used to program the anti-fuse unit according to a programming signal; and a verification unit, comprising a first i...
|
WO/2023/223127A1 |
A semiconductor device having a high storage density is applied in the present invention. This semiconductor device has a first layer and a first insulating material. The first layer has a first oxide semiconductor, first to ninth conduc...
|
WO/2023/221390A1 |
Embodiments of the present disclosure provide an anti-fuse circuit, comprising: an anti-fuse unit; a reading unit for reading the anti-fuse unit to obtain a data signal; a verification control unit disposed between an input end of the re...
|
WO/2023/224095A1 |
This fluorine-containing ether compound is represented by the following formula. R1-R2-CH2-R3[-CH2-R4-CH2-R3]x-CH2-R5-R6 (where R1 and R6 are organic groups having 1-50 carbon atoms, R2 is formula (2-1) or (2-2), R5 is formula (2-3) or (...
|
WO/2023/223673A1 |
An optical recording medium 100 in one aspect of the present disclosure comprises a recording layer 10 and a dielectric layer 20 positioned on the recording layer 10 and including a porous organic structure. The method for recording info...
|
WO/2023/223674A1 |
A recording medium 100 according to an aspect of the present disclosure comprises a recording layer 10 containing a polymer P. The polymer P contains a group G having nonlinear light absorption properties and has a glass transition tempe...
|
WO/2023/221252A1 |
Disclosed in the present invention is a pulse voltage generation apparatus having an adjustable pulse width. The apparatus comprises: a switch control circuit, which is used for generating a control signal; a clock generation circuit, wh...
|
WO/2023/221021A1 |
Memory systems, memory devices, and methods for read reference voltage management are provided. The memory system may include a memory device and a memory controller. The memory device may include one or more memory cells associated with...
|
WO/2023/222458A1 |
The invention relates to improving the quality of an audio and/or video recording which is made by means of a mobile terminal (10), wherein the recording is started by means of a start activity to be manually performed on the mobile term...
|
WO/2023/224890A1 |
In some embodiments, a method includes detecting an incorporation attribute of audiovisual content; analyzing an audio library to determine an audio file that maps to the incorporation attribute; selecting the audio file from the audio l...
|
WO/2023/223126A1 |
Provided is a semiconductor device having a novel configuration. The present invention has: a base die having a first power supply circuit that generates a first voltage; a first die having a second power supply circuit that generates a ...
|
WO/2023/223151A1 |
The present invention relates to a new process for the production of a phonograph disc for analog storing, recording and/or reproduction of a sound content, as well as to a phonograph disc obtainable by means of the aforementioned process.
|
WO/2023/225384A1 |
Disclosed herein are computer-implemented devices, systems, and methods of sanitizing a transcript. In an example, such a method includes selecting a transcript to be sanitized, identifying potential redactions to be made in the transcri...
|
WO/2023/221342A1 |
Disclosed in the present invention are a DDR dual-in-line memory module for correcting an error by using a data buffer, an operation method for the DDR dual-in-line memory module, and a memory system. The DDR dual-in-line memory module c...
|
WO/2023/221219A1 |
The present application relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate having a first surface; a plurality of transistors located on the first surface and arra...
|
WO/2023/223692A1 |
A nonlinear absorbing material in one aspect of the present disclosure includes a compound represented by the following formula (1). In formula (1), R1 to R12, independently of each other, represent groups containing at least one atom se...
|
WO/2023/223574A1 |
This fixing device comprises: a case body that has an accommodation space for accommodating an object to be fixed on the inside of circumferential wall parts standing from a bottom wall part; a pair of retaining parts that are rotatably ...
|
WO/2023/222533A1 |
The invention provides a resistive memory comprising: - a layer comprising a titanium-based material (11); - a second layer comprising a first phase-change material (12); and - a first electrode (13) and a second electrode (14) which are...
|
WO/2023/221196A1 |
The present disclosure relates to the technical field of semiconductors. Disclosed are an address mapping relationship determination method and apparatus, and a storage medium. The address mapping relationship determination method compri...
|
WO/2023/224093A1 |
This fluorine-containing ether compound is represented by the following formula. R1-CH2-R2[-CH2-R3-CH2-R2]x-CH2-R4 (Where: R1 and R4 are terminal groups which include 2 or 3 polar groups, in which each polar group bonds to a different ca...
|
WO/2023/221597A1 |
The present application discloses a storage array and a working method for the storage array. The storage array comprises a plurality of memory cells, a plurality of word lines extending in a row direction, a plurality of bit lines exten...
|
WO/2023/221389A1 |
An anti-fuse circuit, comprising: an anti-fuse unit (10); a programming circuit (20), connected to the anti-fuse unit (10), the programming circuit (20) being used for programming the anti-fuse unit (10) according to a programming contro...
|
WO/2023/221729A1 |
Disclosed are a ferroelectric memory and a control apparatus therefor, a method for improving the durability of the ferroelectric memory, and a device. The control apparatus for the ferroelectric memory comprises a signal control unit (9...
|