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WO/2024/062539A1 |
This memory device, in which in a plan view on a substrate, a page is formed by a plurality of memory cells arranged in the row direction and a plurality of the pages are arranged in the column direction, is characterized in that: the me...
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WO/2024/060478A1 |
The embodiments of the present disclosure disclose a data sampling circuit, a delay detection circuit and a memory. The data sampling circuit comprises a first signal path and a second signal path. The first signal path is configured to ...
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WO/2024/060325A1 |
A decoding circuit (10), a decoding method and a semiconductor memory. The decoding circuit (10) comprises a decoding module (11) and a register module (12). The decoding module (11) is configured to perform decoding processing on an ini...
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WO/2024/060219A1 |
In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through th...
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WO/2024/060555A1 |
The application discloses a chip test method and apparatus, a chip and a computer readable storage medium. The method comprises: a main controller sends a test instruction to each sub-controller in a storage built-in self-test circuit; a...
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WO/2024/058321A1 |
The present invention relates to a memory device including memory cells in which data is stored by the operation of word lines and bit lines, the memory device comprising: a first switch which has one end connected to a bit line connecte...
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WO/2024/055358A1 |
A data processing method, an electronic device, and a computer readable storage apparatus. The method comprises: determining a target layer corresponding to a target storage unit; and operating a storage unit in a non-target layer to imp...
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WO/2024/055832A1 |
Provided in the present disclosure are a non-volatile memory and an erasing method therefor, and a computer system. The non-volatile memory comprises a first area, which needs to be erased, and a second area, which does not need to be er...
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WO/2024/059428A1 |
A device includes a memory configured to store data corresponding to a media stream including video recorded at a first frame rate and multiple audio segments includes the multiple audio segments include one or more first audio segments ...
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WO/2024/058909A1 |
Technology is disclosed for programmatically determining, for a segment of a meeting recording, a user-specific adaptive playback speed, and generating a time-stretched segment playable at the adaptive playback speed. The adaptive playba...
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WO/2024/055685A1 |
The present application relates to the technical field of semiconductor chips, and provides a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device, which improve the anti-interference capability of capac...
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WO/2024/055611A1 |
The present application relates to the technical field of firmware emulation, and in particular to a fault site backtracking method based on firmware emulation, and a device and a readable storage medium. The method comprises: upon recei...
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WO/2024/055484A1 |
The embodiments of the present disclosure provide a programmable storage array, a programming method and a semiconductor memory. The programmable storage array comprises a plurality of storage units. Each storage unit comprises a first t...
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WO/2024/057519A1 |
In the present invention, a first string includes a first memory cell transistor, one end of the first string being connected to a first wire, the other end being connected to a second wire. A second string includes a second memory cell ...
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WO/2024/057114A1 |
A 3D compute-in-memory accelerator system (100) and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores (102), each in-memory core including multiple...
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WO/2024/055373A1 |
Embodiments of the present disclosure relate to the technical field of semiconductors, and provide a voltage regulating circuit and a memory thereof. The voltage regulating circuit comprises: a reference voltage generation module, config...
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WO/2024/057947A1 |
Provided are a magnetic recording medium and a magnetic recording cartridge. An average thickness of the magnetic recording medium tT is tT ≦ 5.3 μm, and a width of the magnetic recording medium is stabilized in 24 minutes or less a t...
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WO/2024/055655A1 |
Disclosed in the present invention is a memory read-write verification method, comprising: firstly, performing margin verification on all IOs of a memory according to input data, and according to a verification result, acquiring read-out...
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WO/2024/055394A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system, and a storage apparatus. The data receiving circuit comprises: a decision feedback equalization module, which is configured to e...
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WO/2024/058877A1 |
A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data regist...
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WO/2024/057941A1 |
A semiconductor memory device (1) comprises: a first pull-down N-channel MOS transistor (21) having a drain connected to a word line (20), a source connected to a ground line, and a gate connected to a first node (91); a first series-con...
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WO/2024/057529A1 |
A semiconductor device according to an embodiment includes: an operational amplifier that has a first input terminal, a second input terminal, and an output terminal, and that outputs a first voltage from the output terminal; a first res...
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WO/2024/058042A1 |
This recording device records data to a non-volatile storage device in a recording mode in which the lowest recording speed is guaranteed. The non-volatile storage device has a memory that performs data recording compliant with NVMe stan...
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WO/2024/054303A1 |
Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory a...
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WO/2024/050926A1 |
Embodiments of the present disclosure provide a data processing structure, a semiconductor structure and a memory. The data processing structure comprises a data sampling module, the data sampling module comprises a logic module and a co...
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WO/2024/053014A1 |
This memory device having, on a substrate in a plan view, a plurality of pages which are each formed by a plurality of memory cells arrayed in the row direction and which are arrayed in the column direction is characterized in that: the ...
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WO/2024/051658A1 |
A shift register unit and a display panel. The shift register unit comprises: a first control circuit (10), a second control circuit (20), a third control circuit (30), and an output circuit (40), wherein the first control circuit (10) i...
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WO/2024/054888A1 |
The subject technology receives frames of a source media content. The subject technology detects from the frames of the source media content, a first gesture indicating a cut point at a particular frame of the source media content, the c...
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WO/2024/050905A1 |
Embodiments of the present disclosure provide a mode register setting code generation circuit and method, a circuit and method for setting a mode register, and a memory. The mode register setting code generation circuit comprises: at lea...
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WO/2024/054280A1 |
The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determine...
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WO/2024/053740A1 |
Provided is a glass for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproducing device that is an amorphous glass that has a B2O3 content of 0.10-2.00 mol% inclusive, a Na2O content of 1...
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WO/2024/053176A1 |
The present invention provides a sputtering target which enables a magnetic layer of a magnetic recording medium to maintain high coercivity, while being capable of improving magnetic separation between magnetic particles. This sputterin...
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WO/2024/053056A1 |
Provided is glass for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproduction device, said glass being amorphous glass with a B2O3 content of 0.10-2.00 mol%, a Na2O content of 1.00-6.00...
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WO/2024/053015A1 |
The present invention provides a memory device in which a page is formed from a plurality of memory cells arranged in a row direction and a plurality of pages are arranged in a column direction on a substrate in a plan view. The memory c...
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WO/2024/054317A1 |
Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory I...
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WO/2024/050689A1 |
A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a periphe...
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WO/2024/053741A1 |
Provided is a glass for a magnetic recording medium substrate, the glass being amorphous glass having a temperature T1 of 1600℃ or lower at a viscosity of 102.0 dPa·s and also having a specific elastic modulus of 34.0 MNm/kg or higher.
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WO/2024/052072A1 |
A track and hold circuit (100) for sampling an input signal, the track and hold circuit (100) comprising a first stage (200) and a second stage (300) and being arranged to operate alternately in a track mode and a hold mode. The first st...
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WO/2024/054316A1 |
Disclosed wherein stacked memory dies that utilize a mix of high and low operational temperature memory and non-volatile based memory dies, and chip packages containing the same. High temperature memory dies, such as those using non-vola...
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WO/2024/054276A1 |
An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The contro...
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WO/2024/054755A2 |
Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configur...
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WO/2024/052256A1 |
The invention relates to a benzopyrylium dyestuff of formula (I), wherein R200,R201, R202, R203, R204, R205, R206, R207 and R208 each independently represent hydrogen, C1- to C16-alkyl, C4- to C7-cycloalkyl C7- to C16-aralkyl, C6- to C10...
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WO/2024/054309A1 |
Mitigating or managing an effect known as "rowhammer" upon a DRAM device may include a memory controller receiving an activation count threshold value from the DRAM device. The memory controller may detect row activation commands directe...
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WO/2024/048955A1 |
According to an embodiment, an electronic device (101) may comprise: at least one microphone (250), at least one speaker (255), a display (160), and at least one processor (120). The at least one processor may be configured to output a r...
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WO/2024/047454A1 |
The present invention provides a highly integrated and reliable semiconductor device. A back gate of a second transistor is electrically connected to a control signal line that provides a control signal for controlling the threshold volt...
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WO/2024/049141A1 |
An electronic device according to one embodiment can identify, from an application processor, a request for encrypting data; encrypt the data on the basis of an ARC included in a mapping table on the basis of the request; acquire, on the...
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WO/2024/046230A1 |
A memory training method, comprising: obtaining training data, and writing the training data into an external memory particle according to an address signal; reading the training data from the external memory particle; obtaining a verifi...
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WO/2024/045263A1 |
Embodiments of the present disclosure provide a control circuit and a semiconductor memory. The control circuit is connected to a sensitive amplification circuit, and the control circuit comprises a pre-charging control module and a powe...
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WO/2024/049531A1 |
To reduce spikes in the current used by a NAND memory die, different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of t...
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WO/2024/045354A1 |
The present disclosure relates to the field of the design of semiconductor circuits. Provided are a clock architecture of a memory, and a memory. The clock architecture of the memory comprises: an on-chip system, which is configured to g...
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