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WO/2024/049532A1 |
To reduce spikes in the current used by a NAND memory die, different ramp rates are used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in a multi-level cell (MLC) for...
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WO/2024/049524A1 |
An apparatus is provided that includes a block of memory cells having a NAND string that includes a first select transistor, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an eras...
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WO/2024/049732A1 |
A pulse generator circuit (210) includes a charge pump (114) having a charge pump output. A voltage divider (R1/R2) is coupled to the charge pump output. The voltage divider (R1/R2) has a voltage divider output. An error amplifier (116) ...
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WO/2024/045262A1 |
Disclosed in embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises: a plurality of active regions; a bit line selection unit, comprising a first gate, a second gate, a thi...
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WO/2024/049533A1 |
To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels followi...
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WO/2024/049750A1 |
A control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. Rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. Row...
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WO/2024/045218A1 |
The present disclosure relates to the field of semiconductor circuit design, and in particular to a monitoring circuit, a refreshing method, and a memory. The monitoring circuit comprises: a sampling module for sampling an initial addres...
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WO/2024/049529A1 |
Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected...
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WO/2024/045733A1 |
A semiconductor structure manufacturing method, a semiconductor structure and a semiconductor device. The method comprises: providing a substrate (1), and separately forming on the substrate (1) a bit line structure (210), a capacitor st...
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WO/2024/045219A1 |
The present disclosure relates to the field of semiconductor circuit designs, and particularly relates to a monitoring circuit, a refreshing method, and a memory. The monitoring circuit comprises: a sampling module, which samples an init...
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WO/2024/045264A1 |
Disclosed in the embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises at least one sub-wordline driver, wherein the sub-wordline driver comprises: a plurality of first ac...
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WO/2024/049683A1 |
A memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data widths (i.e., number of data signals) allocated to each channel are configurable such that a given group of data input/output (I/O) sign...
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WO/2024/045260A1 |
The present disclosure relates to the field of semiconductor circuit design, in particular to a monitoring circuit, a refreshing method, and a memory. The monitoring circuit comprises: a sampling module for sampling an initial address to...
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WO/2024/050265A1 |
A memory device enables write operations with an extended write data window. In a first type of write operation, the memory device receives a merged row/column command at an input interface. The memory device initiates a row operation (e...
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WO/2024/049542A1 |
Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization...
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WO/2024/049715A1 |
An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can ...
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WO/2024/045113A1 |
A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a u...
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WO/2024/045267A1 |
A sense amplifier (100) control method (200) and an electronic device using the control method. The sense amplifier (100) control method (200) comprises, according to a time sequence, an idle stage, an offset cancellation stage, a charge...
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WO/2024/041748A1 |
A connector (100, 102) is provided for generating a biological structure (400, 500, 600, 700) comprising: a protein backbone (106); a first reactive interactor (108) arranged towards a first end of the protein backbone (106) and configur...
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WO/2024/041607A1 |
The present disclosure provides a multi-state one-time programmable memory circuit, comprising a memory cell and a programming voltage driving circuit. The memory cell comprises a metal oxide semiconductor field effect storage transistor...
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WO/2023/245762A9 |
A memory chip test method and apparatus (500), and a medium and an electronic device (600). The memory chip test method comprises: sending a mode register write command to a memory chip, and controlling the memory chip to enter a read-wr...
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WO/2024/043967A1 |
A heat‑assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole that has a recess in the NFT-facing ...
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WO/2024/041708A1 |
The invention relates to a method for storing modifiable information in a secure manner against falsification using a continuously expandable data volume of superimposed data sets, wherein a first data set contains the modifiable informa...
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WO/2024/040758A1 |
The present disclosure relates to the technical field of semiconductor circuit design, and provides a voltage generation circuit and a memory. The voltage generation circuit comprises: a voltage output module, configured to receive a ref...
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WO/2024/041048A1 |
A semiconductor device includes a ferroelectric random-access memory (FeRAM) cell. The FeRAM includes a ferroelectric dielectric that is annealed to attain its ferroelectric phase by an induced current flow and heating process. The curre...
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WO/2024/040694A1 |
The present disclosure relates to the technical field of semiconductors and provides a memory and a memory system thereof. The memory comprises storage blocks and a plurality of bit lines corresponding to the same storage blocks; sense a...
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WO/2024/040693A1 |
The embodiments of the present disclosure provide a delay-locked loop and a memory. The delay-locked loop comprises: a preprocessing module, which is configured to receive an initial clock signal, preprocess the initial clock signal, and...
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WO/2024/042386A1 |
Provided are a tape guide roller and tape drive having a guide roller having magnets and bushings to stabilize a roller barrel for a tape medium. The tape guide roller has a roller barrel extending around a vertical axis. The tape medium...
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WO/2024/040432A1 |
Provided in the embodiments of the present disclosure are a display panel, a display device, and a control method for a display panel. The display panel comprises: a base substrate; a plurality of sub-pixels; a plurality of gate lines, w...
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WO/2024/044377A1 |
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel p...
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WO/2024/040699A1 |
Disclosed in the present application are a spin-wave-unit-based in-memory computing array structure and a control method therefor, which relate to the field of integrated circuits. The spin-wave-unit-based in-memory computing array struc...
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WO/2024/044056A1 |
One example includes an integrated circuit (100) with a sense amplifier (105) that includes a first inverter (110) having a first positive power terminal, a first input and a first output; and a second inverter (115) having a second posi...
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WO/2024/040569A1 |
Methods, systems, and devices for data handling during a reflow operation are described. The method may include a memory system receiving first signaling indicating that a reflow operation is to be performed on the memory system and dete...
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WO/2024/040926A1 |
The present invention provides a storage array, and an interconnection structure thereof and an operation method therefor. The storage array comprises: a plurality of bit lines, wherein one row is provided with two bit lines, comprising ...
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WO/2024/036881A1 |
The present invention belongs to the technical field of testing or measurement of semiconductor devices in a manufacturing or processing process. Disclosed are a reconfigurable MBIST method based on an adaptive March algorithm. An adapti...
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WO/2024/036796A1 |
A write leveling circuit applied to a memory, and a control method and control apparatus for the write leveling circuit. The write leveling circuit comprises: a write signal generation unit (21), which is configured to perform delay proc...
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WO/2024/039417A1 |
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers t...
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WO/2024/037097A1 |
The present application relates to the technical field of storage, and provides a ferroelectric memory and a terminal, which can improve the strength and reading efficiency of a read signal in a reading phase, and reduce the area of the ...
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WO/2024/039431A1 |
Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines i...
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WO/2024/036719A1 |
Embodiments of the present disclosure provide a data receiving circuit and a memory. The circuit comprises: a voltage generation circuit configured to output a first reference voltage signal and a second reference voltage signal in a fir...
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WO/2024/039440A1 |
A lubricant adheres to a magnetic recording medium via at least one of chemisorption or bonding, and contains a perfluorinated polyether attached to or terminated with a functional group that is phosphonic acid, silanol or carboxylic aci...
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WO/2024/037524A1 |
Embodiments of present invention provide a phase change memory (PCM) device. The PCM device includes a first PCM cell with the first PCM cell including an L-shaped phase change element, the L-shaped phase change element having a horizont...
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WO/2024/039486A1 |
An effect known as "rowhammer" may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window...
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WO/2024/036725A1 |
Embodiments of the present invention provide a monitoring circuit and a storage system. The monitoring circuit comprises a voltage detection module and a logic circuit module. The voltage detection module is configured to: detect whether...
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WO/2024/039592A1 |
Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory chip is disclosed. The IC memory chip includes clock receive circuitry to receive a clock signal and...
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WO/2024/037525A1 |
A ferroelectric random-access memory (FeRAM) cell (10) is provided. The FeRAM cell (10) includes a vertical channel (310) between a bottom source/drain region and a top source/drain region (630); a gate oxide (320) surrounding the vertic...
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WO/2024/038786A1 |
Provided are a magnetic recording medium and a magnetic recording cartridge. An average thickness of the magnetic recording medium tT is tT ≦ 5.3 μm, a ratio (A2/A1) of an average creep slope A2 at a temperature of 32 °C and a humidi...
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WO/2024/036876A1 |
Disclosed in the embodiments of the present disclosure is a memory. The memory comprises at least one array area, the array area comprising a storage body area, a first latch area and a second latch area, wherein the first latch area is ...
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WO/2024/036724A1 |
A storage system and an electronic device, which relate to the technical field of semiconductors. The system comprises: a substrate (11); a memory controller (12) arranged on the substrate (11); and a memory module (13) arranged on the s...
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WO/2024/036827A1 |
Embodiments of the present application provide a memory and a manufacturing method therefor, and a read-write control method. In the memory provided in the embodiments of the present application, one source line is provided to electrical...
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