FERROELECTRIC MEMORY AND TERMINAL

WIPO Patent Application WO/2024/037097

A1

The present application relates to the technical field of storage, and provides a ferroelectric memory and a terminal, which can improve the strength and reading efficiency of a read signal in a reading phase, and reduce the area of the ferroelectric memory. The ferroelectric memory comprises a bit line, an i-th plate line, a multiplexer, a comparator, and multiple ferroelectric memory cells. Each ferroelectric memory array of the multiple ferroelectric memory cells comprises a number m of columns of ferroelectric memory cells arranged in an array, and a ferroelectric memory cell comprises a ferroelectric capacitor and a first transistor. In any row, a ferroelectric capacitor of an (m*n+i)-th column ferroelectric memory cell is electrically connected to the i-th plate line, and in the reading phase, each plate line in the i-th plate line inputs a high level to the ferroelectric memory cell in a time-division mode, m being an integer greater than or equal to 2, n being an integer greater than or equal to 0, and i being a positive integer less than or equal to m. Each column of ferroelectric memory cells is electrically connected to one bit line, and each m bit lines are electrically connected to the same multiplexer. Each comparator is electrically connected to one multiplexer.

LI HAO (CN)
JIA XIUFENG (CN)
ZHANG MIN (CN)
ZHAO JIE (CN)
ZHANG HENG (CN)
YANG XICHAO (CN)
LV HANGBING (CN)
XU JEFFREY JUNHAO (CN)

PCT/CN2023/096767

February 22, 2024

May 29, 2023

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HUAWEI TECH CO LTD (CN)

G11C11/22

CN101777377A	2010-07-14
CN111801737A	2020-10-20
US20040015643A1	2004-01-22

BEIJING RUN ZEHENG INTELLECTUAL PROPERTY LAW FIRM (CN)

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