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WO/2023/245923A1 |
The present disclosure provides a memory device and a ZQ calibration method. The memory device comprises: a master chip and a plurality of slave chips, the master chip and the slave chips being each provided with a first transmission end...
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WO/2023/245792A1 |
Embodiments of the present disclosure provide a refresh control circuit and a method therefor, and a memory. The refresh control circuit comprises: an address output module, configured to output an address to be refreshed signal, the add...
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WO/2023/245746A1 |
The embodiments of the present disclosure relate to a word line drive circuit, a word line driver, and a storage apparatus. The word line drive circuit comprises: at least two sub-word line drivers, wherein each sub-word line driver is c...
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WO/2023/247554A1 |
The invention relates in a first aspect to a master plate for industrial hologram replication, comprising a flat and planar composite pane having a thick glass pane as a carrier for minimizing the deflection of the master plate and a thi...
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WO/2023/245747A1 |
Embodiments of the present disclosure relate to a word-line driver and a storage apparatus. The word-line driver comprises: a PMOS region, comprising first active regions extending in a first direction, wherein each of the first active r...
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WO/2023/249721A1 |
An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logi...
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WO/2023/245921A1 |
Provided in the present disclosure are a memory device and a ZQ calibration method. The memory device comprises: two calibration resistor interfaces, which are connected to the same ZQ calibration resistor; a first master chip, a plurali...
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WO/2023/248080A1 |
The invention concerns a method for characterizing a magnetic device including a plurality of binary nanomagnets, which may be arranged in an array, comprising (i) providing a magnetic device, which is a binary nanomagnetic array, compri...
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WO/2023/250030A1 |
Technologies and implementations for a voltage management circuit. The voltage management circuit may be configured to facilitate management of behavior of electronic devices including management of process corners associated with semico...
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WO/2023/247553A1 |
The invention relates to a magnetic card (2) reader (1), which comprises: - an electronic card (5); - a magnetic reading head (6) which is intended to read data contained in a magnetic strip (9) of a magnetic card and to transmit these d...
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WO/2023/098927A9 |
The present disclosure provides a display substrate and a display apparatus. The display substrate comprises: a base substrate, comprising a display area and a peripheral area located on at least one side of the display area; a pixel arr...
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WO/2023/245780A1 |
Embodiments of the present disclosure relate to the field of semiconductor testing, and in particular to a test method, a test structure, and a memory. The test structure comprises: an instruction storage unit used for storing a test com...
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WO/2023/245728A1 |
The present disclosure provides a semiconductor structure and a manufacturing method therefor, a memory and an operation method therefor. The semiconductor structure comprises: a substrate, the substrate having a plurality of active regi...
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WO/2023/248415A1 |
A memory device in which, in a plan view on a substrate, a page is configured from a plurality of memory cells arranged in a row direction, and a plurality of pages are arranged in a column direction, the memory device being characterize...
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WO/2023/246057A1 |
A linear motor driving method and device, and a storage medium. The method comprises: obtaining a time domain audio waveform for driving the audio data of the linear motor and a working frequency of the linear motor to be driven; process...
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WO/2023/247645A1 |
An example one-time programmable (OTP) memory device is provided. The OTP memory device include a passivation layer. A top metal layer is positioned below the passivation layer. The top metal layer includes one or more holes configured t...
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WO/2023/245667A1 |
Provided are a shift register unit, a gate driving circuit, a display apparatus, and a driving method. The shift register unit comprises: a first control circuit (01), which is configured to control signals of a first node (N1) and a sec...
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WO/2023/245751A1 |
Embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device. The data receiving circuit comprises: a first amplification module configured to receive a data signal, a first refere...
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WO/2023/249717A1 |
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared b...
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WO/2023/207216A9 |
A shift register (ASG), a gate drive circuit (141), a display panel (10) and an electronic device. The shift register (ASG) comprises: a node control module (142), which is electrically connected to a first level signal receiving end (VG...
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WO/2023/245942A1 |
An SSD finite window data deduplication identification method and apparatus, a computer device, and a storage medium. The method comprises: if a command is a write command, allocating a write buffer area and receiving data from a host, d...
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WO/2023/249738A1 |
Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods are disclosed. The memory arra...
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WO/2023/250032A1 |
Technologies and implementations for a wake-up circuit. The wake-up circuit may be configured to reduce a peak value of current draw during waking up of an electronic device. The reduction of the peak value of current draw facilitates a ...
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WO/2023/249703A1 |
The present disclosure generally relates to a magnetic recording head comprising a spintronic device. The spintronic device is disposed between a main pole and a trailing shield of the magnetic recording head. The spintronic device compr...
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WO/2023/245729A1 |
Provided in the embodiments of the present disclosure are an impedance calibration circuit, an impedance calibration method and a memory. The impedance calibration circuit comprises a parameter module, an initial value generation module ...
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WO/2023/245765A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a dat...
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WO/2023/245750A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a dat...
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WO/2023/245863A1 |
The present disclosure provides a data receiving circuit, a data receiving system, and a storage device. The data receiving circuit comprises: a receiving module configured to receive a data signal and a reference signal, compare the dat...
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WO/2023/245920A1 |
Provided in the present disclosure are a word line driving circuit, a word line driver and a storage apparatus. The word line driving circuit comprises: at least two sub-word-line drivers, which are connected to a main word line and a su...
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WO/2023/249719A1 |
The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memo...
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WO/2023/245922A1 |
The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device comprises a master chip and a plurality of slave chips each provided with a first transm...
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WO/2023/245822A1 |
Embodiments of the present disclosure provide a test structure, a formation method therefor and a semiconductor memory. The test structure comprises multiple word lines and multiple bit lines, and a vertical transistor is formed at the i...
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WO/2023/245925A1 |
Provided are a memory device and a ZQ calibration method. The memory device comprises: two calibration resistor interfaces, which are connected to the same ZQ calibration resistor; and a first master chip, first slave chips, a second mas...
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WO/2023/245749A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a dat...
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WO/2023/245727A1 |
Embodiments of the present application provide a random data generation circuit and a read-write training circuit. The random data generation circuit comprises: a first shift register and a second shift register, the first shift register...
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WO/2023/250394A1 |
A digital neutron and photon track dosimeter based on three-dimensional Not-And (3D NAND) flash memory may be provided. A plurality of logical addresses respectively associated with a plurality of cells in a 3D NAND flash memory that hav...
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WO/2023/245785A1 |
Embodiments of the present disclosure provide a semiconductor device, and a data processing circuit and method. A chip select signal and a plurality of command signals are received by means of an input end of the data processing circuit,...
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WO/2023/249826A1 |
A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory access...
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WO/2023/244866A1 |
A method for capturing real-time motion data events from a remotely deployed far edge compute node on a remote asset, such as a racing vehicle, allows for real-time motion simulation of a racing experience. In the method, incoming audio ...
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WO/2023/240513A1 |
Embodiments of this application provide a shift register, a shift register circuit, a display panel, and an electronic device. The shift register includes an input circuit, a bootstrapping circuit, and an output circuit, wherein the inpu...
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WO/2023/241433A1 |
A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the...
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WO/2023/025035A9 |
Aspects of the present disclosure relate to a method for reducing repositioning time within tape systems. A request to reposition to a target file within a tape medium can be received. A determination can be made that a previous command ...
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WO/2023/245204A1 |
The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode; a second electrode comprising a first conductive material; and a switching oxide layer posi...
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WO/2023/245205A1 |
The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, an RRAM device includes: a first electrode including a metal nitride; a second electrode comprising a first conductive material; and a ...
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WO/2023/240676A1 |
Provided in the embodiments of the present disclosure are a data processing circuit and method, and a semiconductor memory. The data processing circuit comprises a receiving module, a first power supply module and a processing module, wh...
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WO/2023/240767A1 |
Provided in the present disclosure are a memory chip evaluation method and apparatus, a memory chip access method and apparatus, and a storage medium. The evaluation method comprises: testing a preset number of memory chips under test; c...
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WO/2023/241295A1 |
Disclosed in the embodiments of the present application are a ferroelectric memory and a manufacturing method for a ferroelectric memory. The ferroelectric memory comprises a storage array, the storage array comprises X rows * Y columns ...
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WO/2023/240728A1 |
The present invention relates to the technical field of storage. Provided are a programmable memory and a driving method therefor. The programmable memory comprises: a plurality of anti-fuse units, a plurality of word lines and a control...
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WO/2023/244335A1 |
A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of a...
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WO/2023/242665A1 |
Provided is a semiconductor device having a novel configuration. This semiconductor device comprises a first element layer, and a plurality of second element layers on each of which a temperature detection circuit, a voltage generation c...
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