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WO/2024/007521A1 |
Embodiments of the present disclosure provide a memory and an access method therefor, and an electronic device. The memory comprises at least one memory array, at least one control circuit, and a plurality of read word lines and read bit...
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WO/2024/007543A1 |
Embodiments of the present application provides a storage unit and a memory and a control method therefor. In the storage unit provided by the embodiments of the present application, a first electrode of a first transistor is configured ...
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WO/2024/007363A1 |
Disclosed in embodiments of the present invention are an anti-fuse circuit and a circuit test method. The anti-fuse circuit comprises: a first transistor; and at least one parasitic transistor and at least one parasitic triode which are ...
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WO/2024/010721A1 |
A suspension assembly includes a load beam, a base plate connected to the load beam, and a single actuator disposed in an opening of the base plate. The single actuator is formed of a crystal material that expands along a first axis and ...
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WO/2024/007418A1 |
A memory cell, an NAND string, a memory cell array, and a data access method. The memory cell comprises a first transistor and a second transistor; the first transistor comprises a first electrode, a second electrode, and two independent...
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WO/2024/007377A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, comprising: an amplification unit, w...
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WO/2023/184281A9 |
An inspection parameter analysis method and apparatus. The method comprises: acquiring a plurality of groups of first inspection parameters of a product, wherein the first inspection parameters comprise inspection parameters of a plurali...
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WO/2024/007360A1 |
Disclosed in the embodiments of the present disclosure are an anti-fuse unit structure, an anti-fuse array and an operation method therefor, and a memory. The anti-fuse unit structure comprises: a first anti-fuse transistor, which has a ...
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WO/2024/007914A1 |
The present application discloses an SRAM control system, a method, an FPGA chip, and electronic equipment. The SRAM control system comprises a main control module, at least one SRAM control module, and a bus module, the bus module being...
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WO/2024/007391A1 |
A data transmission structure, a data transmission method, and a memory, relating to the field of semiconductor circuit design. The data transmission structure comprises: a data transmission module (100) configured to generate second dat...
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WO/2024/007399A1 |
A memory (10), a control apparatus, a clock processing method, and an electronic device. A clock processing circuit (20) in the memory (10) comprises: a duty ratio module (21), which is configured to adjust the duty ratio of a data clock...
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WO/2024/009665A1 |
This servo pattern recording head comprises a plurality of magnetically separated head cores, and a plurality of gap patterns that are respectively formed on surfaces of the plurality of head cores and record a plurality of servo pattern...
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WO/2024/007398A1 |
A control apparatus (10), a memory (20), a signal processing method, and an electronic device (50). The control apparatus (10) comprises: a receiving module (11), which is configured to receive a read clock signal from a memory, and outp...
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WO/2024/001405A1 |
Disclosed in the embodiments of the present application are an audio processing method and apparatus, and a chip, an electronic device and a storage medium. The method is applied to an electronic device, and the method comprises: perform...
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WO/2024/000811A1 |
Disclosed in the embodiments of the present disclosure are a clock control circuit and a semiconductor memory. The clock control circuit comprises a first decoding path, a second decoding path and a clock gating circuit, wherein the firs...
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WO/2024/001332A1 |
Provided in the present application are a multi-port memory, and a reading and writing method and apparatus for a multi-port memory. The multi-port memory comprises N write ports, one write controller, K write buffers and one memory bloc...
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WO/2024/005932A1 |
The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprise one or more GeXNiFe layers, where at least one GeXNiFe layer is disposed in contact ...
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WO/2024/006026A1 |
A phonograph record player including a speaker enclosure within the record player that is mechanically insulated from the phonograph components to reduce vibrations from the speakers to the phonograph components. One or more coupling mec...
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WO/2024/000462A1 |
Provided are a display substrate and a display apparatus. The display substrate comprises: a pixel circuit (PE) and a scanning drive circuit, wherein the pixel circuit comprises: a writing transistor and a scan signal line (GL), the scan...
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WO/2024/000910A1 |
A data input verification method and a data input verification structure. The data input verification method comprises: generating a randomly combined input character string (101); on the basis of the input character string and an analog...
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WO/2024/006302A2 |
A semiconductor device includes a floating gate that can be charged in a nonvolatile manner. The floating gate is also structured as an optical waveguide, and may be optically coupled to a photonic circuit, such as an interferometer.
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WO/2024/000630A1 |
The present disclose provides a sense amplifier and a semiconductor memory. The sense amplifier comprises: a power source module, which is provided with an output end, and is used for acquiring temperature data of the power source module...
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WO/2024/000640A1 |
Provided in the present disclosure are a sense amplifier and a semiconductor memory. The sense amplifier comprises a control module provided with an input end and an output end and an amplification module. The control module is configure...
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WO/2024/000651A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, which comprises first active...
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WO/2024/000618A1 |
Embodiments of the present disclosure provide a memory cell detection method and a device. The method comprises: writing first data to a memory cell; performing first reading on the memory cell, so as to adjust a first voltage of a first...
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WO/2024/000617A1 |
The present disclosure provides a sense amplifier and a semiconductor memory. The sense amplifier comprises: a control module, provided with an input end and an output end, and used for obtaining temperature data of an amplifier module, ...
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WO/2024/001622A1 |
The present application provides a ferroelectric memory, and a reading circuit and method for the ferroelectric memory, wherein the reading circuit comprises a first switching transistor, a second switching transistor, an equalizer and a...
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WO/2024/000646A1 |
Provided in the embodiments of the present disclosure is a semiconductor memory, comprising: an input module, which is configured to receive an address/command input signal; a plurality of redundant modules, which are divided into N sets...
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WO/2024/000625A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises: a first active region; a first gate, located above the first active region, the first active region ...
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WO/2024/005943A1 |
In an implementation, a software application on a computing device directs the device to extract audio data from a media file comprising the audio data and video data, generate a trim proposal based on analysis of speech in the audio dat...
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WO/2023/225772A9 |
The present invention relates to the technical field of integrated circuit testing. Provided are a fully automatic method and system for testing read and write functions of a DRAM storage cell. The method comprises the following steps: a...
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WO/2024/001574A1 |
Provided in the embodiments of the present application is a memory. The memory comprises: a first storage unit, a sensitive amplifier, a first bit line, a second bit line, a first isolator, a second isolator, a third isolator, a fourth i...
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WO/2024/005806A1 |
Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an "angled transistor" if a longitudinal axis of an elongated semiconductor structure...
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WO/2024/005927A1 |
Various illustrative aspects are directed to a data storage device, comprising one or more disks; at least one actuator mechanism configured to position at least a first head proximate to a first disk surface and a second head proximate ...
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WO/2024/001328A1 |
The present application relates to the field of flash-based FPGAs, and discloses a program disturb suppressing configuration control circuit of a flash-based FPGA. Compared with conventional configuration control circuits, in this config...
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WO/2024/006010A1 |
In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affe...
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WO/2024/006848A1 |
An integrated current sensing amplifier with offset cancellation implemented in GaN technology. The current sensing amplifier senses the current flowing through a low side power FET or a high side power FET of a half bridge circuit. The ...
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WO/2024/005140A1 |
The present invention provides a compound which is represented by formula (1). (In the formula, A represents a polymerizable group; n represents an integer of 1 to 3; L represents an optionally branched linking group having a valence o...
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WO/2024/004126A1 |
This domain wall displacement element comprises a first magnetoresistance effect element and a first transistor. A first domain displacement layer of the first domain displacement layer is electrically connected to the first active regio...
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WO/2024/006148A1 |
A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second...
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WO/2024/001894A1 |
Disclosed in the present application is an information verification method. The method comprises: acquiring a fluorescence signal, wherein the fluorescence signal is an electrical signal, which is generated on the basis of a plurality of...
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WO/2024/001703A1 |
Embodiments of the present disclosure relate to a memory apparatus. The memory apparatus comprises: a printed circuit board; an interposer arranged on the printed circuit board; a memory cell group arranged on the interposer; a control u...
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WO/2024/005923A1 |
The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second B...
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WO/2024/005141A1 |
The present invention provides a composition for holographic recording media, the composition being characterized by containing the components (a) to (d) described below, and being also characterized in that the abundance of allophanate ...
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WO/2024/000324A1 |
Some embodiments of the present application relate to the technical field of semiconductors. Provided are a ferroelectric memory array and a preparation method therefor, and a memory and an electronic device, which aim to improve the the...
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WO/2024/000628A1 |
The present disclosure provides a sense amplifier and a semiconductor memory. The sense amplifier comprises: a control module which is provided with an input end and an output end and is used for obtaining temperature data of a writing m...
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WO/2024/005139A1 |
Provided is a method for producing an optical element, wherein a holographic recording medium having a recording layer containing a polymerizable compound and a photopolymerization initiator is subjected to multiple hologram-recording ex...
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WO/2024/000629A1 |
Provided in the present disclosure are a sense amplifier and a semiconductor memory. The sense amplifier comprises a control module, which is provided with an input end and a first output end and is used for acquiring temperature data of...
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WO/2023/249718A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to ap...
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WO/2023/246931A1 |
A memory device, a memory system, and a method thereof are provided. In the method, an N-th programming pulse is applied to a word line coupled to memory cells of the memory device each with a target programming state being an i-th progr...
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