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WO/2024/069161A1 |
A phonograph record is formed at least partially from a bioplastic. The bioplastic is preferably PLA, preferably mixed with graphene and/or graphite.
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WO/2024/071392A1 |
This fluorine-containing ether compound is represented by the following formula. R1-CH2-R2(-CH2-R3-CH2-R2)x-CH2-R4 (In the formula, x represents an integer of 1 or 2; R2 represents a perfluoropolyether chain; R3 is represented by formula...
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WO/2024/066533A1 |
The present invention provides an information processing method of a chip assembly. The chip assembly comprises a chip, an information memory, and a one-time programmable memory eFUSE. The method comprises: encrypting a plaintext of conf...
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WO/2024/073681A1 |
A crossbar circuit including a crossbar array and a periphery circuit is provided. A resistive random-access memory (RRAM) device of the crossbar array includes a bottom electrode fabricated on a first interconnect layer; a top electrode...
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WO/2024/071982A1 |
An electronic device is disclosed. The electronic device comprises a communication interface and at least one processor for inducing: a first audio to be output if the first audio and a signal corresponding to a first play start for the ...
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WO/2024/071399A1 |
This fluorine-containing ether compound is represented by the following formula. R1-CH2-R2[-CH2-R3-CH2-R2]x-CH2-R4 (x is 1 or 2. R2 is a perfluoropolyether chain. R3 is represented by formula (2). R1 and R4 are terminal groups having 1-5...
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WO/2024/066917A1 |
The present application relates to the technical field of semiconductor design and manufacturing, and provides a ring inverter, a latch, a storage circuit, a memory, and an electronic device. The ring inverter is manufactured by using ve...
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WO/2024/072258A1 |
A portable radio flash drive, connectable to a computer or smartphone, for storing, transferring and exchanging data, comprising a radio interface for communicating and automatically synchronizing stored data with another such flash driv...
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WO/2024/070554A1 |
The purpose of the invention is to provide: a tape-form magnetic recording medium with which it is possible to correct any change in the width of the magnetic recording medium by adjusting the transport tension of the magnetic recording ...
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WO/2024/072726A1 |
A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, ...
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WO/2024/070953A1 |
Provided is a recording device with which the sealing performance of a gasket having a narrow portion can be improved. The recording device comprises a base 17 in which an internal mechanism 5 is accommodated in a space 3a having an open...
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WO/2024/070719A1 |
Provided is a magnetic recording medium suited for storage and travel in a high temperature environment.　The magnetic recording medium according to the present technology is a tape-shaped magnetic recording medium. In this magnetic rec...
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WO/2024/072498A1 |
A glass sheet configured to be cut into glass substrates for magnetic recording disks is described. The glass sheet includes a first surface. For surface features of the first surface with a feature wavelength of 60 to 500 micrometers (Î...
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WO/2024/066033A1 |
A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The...
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WO/2024/070466A1 |
A recording medium according to the present disclosure which is connected to a host device, said recording medium being equipped with a memory, a control unit for controlling the memory, and an interface unit which communicates with the ...
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WO/2024/070952A1 |
Provided is a cover with which it is possible to improve the sealability of a gasket having a narrow-width section. A cover 19 is installed in an opening 17a in a base 17 of a housing 3 for housing an internal mechanism 5 in a space 3a, ...
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WO/2024/045705A9 |
The present application provides a chip and an electronic device. The chip comprises a data storage area and a sensing area. The magnetic field sensitivity of a first magnetic tunnel junction in the sensing area is higher than that of a ...
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WO/2024/066384A1 |
A magnetic random access memory (MRAM) apparatus includes a magnetic tunnel junction (MTJ) stack; a spin-orbit-torque (SOT) layer that underlies the MTJ stack; and a dielectric pillar that underlies the SOT layer and the MTJ stack. The S...
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WO/2024/065889A1 |
Embodiments of the present invention relate to the technical field of semiconductors, and provide a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate and a magnetic tunnel jun...
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WO/2024/066521A1 |
The embodiments of the present application relate to the technical field of computers. Disclosed are a memory refresh method and apparatus, which can reduce the power consumption of a memory. The method comprises: acquiring target inform...
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WO/2024/066190A1 |
A display apparatus, a gate drive circuit, and a shift register unit and a drive method therefor. The shift register unit comprises an input sub-circuit (1), a first control sub-circuit (2), a second control sub-circuit (3), a third cont...
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WO/2024/069769A1 |
The present disclosure provides a computation device equipped with a first signal line, a first capacitor which is connected to the first signal line, one or more sub-arrays which are connected to the first signal line, and a readout cir...
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WO/2024/065658A1 |
A gate driving circuit and a driving method therefor, and a display panel and a display apparatus. A gate driving circuit (10) comprises M groups of shift register units, wherein each group of shift register units comprises a first shift...
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WO/2024/072971A1 |
A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory,...
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WO/2024/072497A1 |
A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, t...
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WO/2024/065909A1 |
The present disclosure relates to the field of semiconductors, and in particular, to an anti-fuse circuit, structure, array, programming method and memory. The anti-fuse circuit comprises: an anti-fuse, a select transistor and a clamping...
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WO/2024/073231A1 |
Systems, apparatuses, and methods for prefetching data by a display controller are proposed. From time to time, a performance-state change of a memory is performed. During such changes, a memory clock frequency is changed for a memory su...
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WO/2024/072981A1 |
A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit...
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WO/2024/066383A1 |
The embodiments of the present application relate to the field of storage device applications, and disclose a flash memory management method and a flash memory device; the flash memory management method involves: obtaining a logic word l...
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WO/2024/064239A1 |
In some implementations, at least a partial view of a jog wheel user interface (UI) element is displayed on a graphical user interface (GUI). The jog wheel UI element is operable to manipulate one or more secondary elements. In response ...
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WO/2024/064010A1 |
Methods and devices for reading and programming a state of a switch device are presented. The programming of the state of the switch device is performed by providing driving pulses to the switch device. The amplitude and the width of the...
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WO/2024/060405A1 |
A dynamic random access memory test method and device, relating to the technical field of memories. A dynamic random access memory comprises a base substrate (402) and a plurality of memory cells (3062, 3064); each memory cell (3062, 306...
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WO/2024/060367A1 |
The embodiments of the present disclosure provide a memory and a storage system. The memory comprises: a substrate; a control circuit layer, which is located in the substrate, wherein the control circuit layer comprises at least part of ...
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WO/2024/063822A1 |
The present disclosure generally relates partial speed changes to improve in-order data transfer. Rather than determining an ECC decoder on a first available decoder basis, the ECC decoder may be based on the ECC decoder level. A memory ...
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WO/2024/062252A1 |
A motor for a turntable, comprising: a stator comprising a plurality of conductive coils, the conductive coils comprising a plurality of coil windings; and a rotor comprising a plurality of permanent magnets, wherein: the stator and the ...
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WO/2024/064075A1 |
Methods, systems, and media for providing automated assistance during a video recording session are provided. In some embodiments, the method comprises: receiving, at a first user device, user input to initiate a video recording session,...
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WO/2024/063794A1 |
Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a ...
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WO/2024/060315A1 |
Provided in the present disclosure are a built-in self-test method, a built-in self-test apparatus and a semiconductor memory. The method comprises: acquiring temperature data of a storage unit, and according to the temperature data, adj...
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WO/2024/060059A1 |
A memory device includes a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, and a charge control circuit coupled to the memory cell array. The plurality of ...
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WO/2024/060611A1 |
A method of realizing a content-addressable memory (CAM) based on field effect transistors having bipolar characteristics. By inserting a storage layer between a gate dielectric layer and a control gate of a field effect transistor havin...
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WO/2024/063793A1 |
Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling si...
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WO/2024/060323A1 |
Embodiments of the present disclosure provide a counting circuit, a semiconductor memory, and a counting method. The counting circuit comprises a first decoding module and a first counting module, and the first decoding module is connect...
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WO/2024/060365A1 |
Provided in the embodiments of the present disclosure are a word-line driver, and a storage apparatus. The word-line driver comprises: a first holding transistor and a second holding transistor; an active area, comprising a main body por...
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WO/2024/063792A1 |
Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory ce...
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WO/2024/060317A1 |
Embodiments of the present disclosure provide a command decoding circuit and a method thereof, and a semiconductor memory. The command decoding circuit comprises: a clock processing module, which is configured to receive an initial clock...
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WO/2024/060378A1 |
The present disclosure relates to the technical field of memories. Provided are a dynamic random access memory test method and apparatus. A dynamic random access memory comprises a substrate and a plurality of storage units, wherein each...
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WO/2024/060316A1 |
A built-in self-test method and device. The built-in self-test method comprises: acquiring a first initial address of a storage region (110) of data to be written, and masking at least one bit address of the first initial address, so as ...
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WO/2024/061005A1 |
A read processing method and apparatus for an audio and video buffer. The data read-write mode of the audio and video buffer is improved. Consumer modules create respective handles for reading data. Using a read handle as a unique identi...
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WO/2024/062978A1 |
A magnetoresistive element according to one embodiment of the present disclosure comprises a multilayer structure, a memory layer disposed on the multilayer structure and changeable in magnetization direction, a nonmagnetic layer dispose...
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WO/2024/063315A1 |
Disclosed is a three-dimensional memory having a dual junction structure. According to an embodiment, the three-dimensional memory may comprise: gate electrodes spaced apart and stacked in a vertical direction while extending in the hori...
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