Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2024/066033
Kind Code:
A1
Abstract:
A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The memory cell array block is divided into at least two memory cell array subblocks, each memory cell array subblock comprising a number of layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The control logic is coupled to the memory cell array block, and configured to: erase, read or program the memory cell array block using a block mode or a subblock mode, and when the memory cell array block is erased, read, or programmed under the subblock mode, determine, at least based on a state of one of the two memory cell array subblocks, an operation strategy of the other memory cell array subblock.

Inventors:
GUO XIAOJIANG (CN)
Application Number:
PCT/CN2022/136531
Publication Date:
April 04, 2024
Filing Date:
December 05, 2022
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
YANGTZE MEMORY TECH CO LTD (CN)
International Classes:
G11C16/34
Foreign References:
CN113345489A2021-09-03
CN112313747A2021-02-02
US20080219053A12008-09-11
US20130100737A12013-04-25
US20160104533A12016-04-14
US20180068740A12018-03-08
Attorney, Agent or Firm:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD. (CN)
Download PDF: