Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2023/242956
Kind Code:
A1
Abstract:
This memory device includes a page composed of a plurality of memory cells arranged on a substrate in a columnar configuration as seen in a plan view, and hole groups generated by the impact ionization phenomenon are retained inside a channel semiconductor layer by controlling a voltage applied to a first gate conductor layer, a second gate conductor layer, a first impurity region and a second impurity region of each memory cell included in the page. The first impurity layer of the memory cell is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, the other is connected to a plate line, and a page write operation, a page erase operation, and a page read operation are performed by applying a voltage to the source line, bit line, word line, and plate line. The hole groups formed by the impact ionization phenomenon are retained inside the channel semiconductor layer at a first timing during the page write operation, and a page post-write processing operation of annihilating a surplus hole group among the hole groups is performed at a second timing.
Inventors:
SAKUI KOJI (JP)
KAKUMU MASAKAZU (JP)
HARADA NOZOMU (JP)
KAKUMU MASAKAZU (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2022/023825
Publication Date:
December 21, 2023
Filing Date:
June 14, 2022
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SAKUI KOJI (JP)
KAKUMU MASAKAZU (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
KAKUMU MASAKAZU (JP)
HARADA NOZOMU (JP)
International Classes:
G11C11/401; G11C16/04; H01L27/10
Foreign References:
| JP7057032B1 | 2022-04-19 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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