Title:
SEMICONDUCTOR DEVICE AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/231164
Kind Code:
A1
Abstract:
A semiconductor device and a memory. The semiconductor device comprises a pull-up circuit integration area (61), a pull-down circuit integration area (62), and a compensation circuit integration area (63) that do not overlap each other; the semiconductor device further comprises an output circuit; the output circuit comprises: a pull-up circuit (1), a pull-down circuit (2), and a compensation circuit (4); the pull-up circuit (1) is connected to a signal output line (LDQ); the pull-up circuit (1) is located in the pull-up circuit integration area (61); the pull-down circuit (2) is connected to the signal output line (LDQ); the pull-down circuit (2) is located in the pull-down circuit integration area (62); the compensation circuit (4) is used for enhancing the driving capability of an output signal on the signal output line (LDQ); and the compensation circuit (4) is located in the compensation circuit integration area (63). The semiconductor device can reduce parasitic capacitance between a control line connected to the compensation circuit (4) and other structures, thereby facilitating the optimization of the timing of signals on the control line connected to the compensation circuit (4).
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Inventors:
LIU ZHONGLAI (CN)
Application Number:
PCT/CN2022/107184
Publication Date:
December 07, 2023
Filing Date:
July 21, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/40
Foreign References:
| CN112187214A | 2021-01-05 | |||
| CN114242129A | 2022-03-25 | |||
| CN113437962A | 2021-09-24 | |||
| US20180204521A1 | 2018-07-19 |
Attorney, Agent or Firm:
BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)
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