Title:
REFRESH ADDRESS GENERATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/231263
Kind Code:
A1
Abstract:
Disclosed in the embodiments of the present disclosure is a refresh address generation circuit, comprising: a refresh control circuit, a repetitive command processing circuit and an address generator. The refresh control circuit is used for sequentially receiving a plurality of first refresh instructions and performing a plurality of first refresh operations corresponding thereto, and outputting a first clock signal when the number of first refresh operations is less than k. The repetitive command processing circuit is coupled to the refresh control circuit and is used for receiving the first refresh instructions, and outputting an extra refresh flag signal when repetitive instructions appear in the first refresh instructions. The address generator is coupled to the refresh control circuit and the repetitive command processing circuit, pre-stores a first address, and is used for outputting, when the first clock signal is received and the extra refresh flag signal is not received and in response to the first clock signal, an address to be refreshed, or outputting an extra address in response to the extra refresh flag signal when the extra refresh flag signal is received.
Inventors:
GU YINCHUAN (CN)
Application Number:
PCT/CN2022/123849
Publication Date:
December 07, 2023
Filing Date:
October 08, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/406; G11C11/408
Foreign References:
| CN103578526A | 2014-02-12 | |||
| CN114121115A | 2022-03-01 | |||
| CN103426462A | 2013-12-04 | |||
| CN105989870A | 2016-10-05 | |||
| US20120195149A1 | 2012-08-02 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
Download PDF: