Title:
RECEIVING CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/231177
Kind Code:
A1
Abstract:
The present disclosure provides a receiving circuit and a memory. The receiving circuit comprises: an input buffer, configured to receive a first input signal and a second input signal and compare the first input signal with the second input signal, and to output a first output signal and a second output signal, wherein in a differential mode, the first input signal and the second input signal are respectively a first signal and a second signal, and in a single-ended mode, the first input signal is one of the first signal and the second signal, the second input signal is a reference voltage signal, and the first signal and the second signal are complementary to each other; and a conversion module, configured to receive the first output signal and the second output signal and amplify a voltage difference between the first output signal and the second output signal so as to output a first internal signal and a second internal signal.
Inventors:
LIN FENG (CN)
Application Number:
PCT/CN2022/111185
Publication Date:
December 07, 2023
Filing Date:
August 09, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C7/10
Foreign References:
| CN111724833A | 2020-09-29 | |||
| CN110880339A | 2020-03-13 | |||
| CN107785046A | 2018-03-09 | |||
| CN107534440A | 2018-01-02 | |||
| US20110031999A1 | 2011-02-10 |
Other References:
See also references of EP 4307302A4
Attorney, Agent or Firm:
BOXIN CHINA INTELLECTUAL PROPERTY (CN)
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