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WO/2024/091414A1 |
Gate-all-around transistor devices and methods for manufacturing the same are provided. The semiconductor device includes a substrate. The substrate includes a plurality of isolation regions formed in the substrate, the plurality of isol...
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WO/2024/092072A1 |
The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adj...
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WO/2024/086913A1 |
A module has two portions, each portion has two units provides an analog-type attenuator-tuning approach having digital control. Each of the units includes an input, an output, three selectable conductive paths, and an input switching el...
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WO/2024/087514A1 |
A semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate (100), a gate structure (200) and a channel region (300), wherein the substrate (100) comprises a gate trench (110). The cha...
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WO/2024/091179A1 |
This document describes a vertical channel-all-around metal-antiferroelectric-metal-insulator-semiconductor (MAMIS) field effect transistor and a method for manufacturing the same. This application also relates to a semiconductor device ...
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WO/2024/089963A1 |
The present invention provides a method for filling up a trench, which is formed in a silicon substrate and has a small opening width and a large aspect ratio, by means of high-rate epitaxial growth, while preventing closing of the openi...
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WO/2024/091606A1 |
Provided herein are methods and systems for subharmonic tags including a single antenna having a reactive input impedance and a set of lumped components coupled to the antenna, the lumped components having a frequency-dependent input imp...
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WO/2024/087174A1 |
The embodiments of the present disclosure provide a thin film transistor device and a manufacturing method therefor, a compound etching solution, and an array substrate. The method comprises: forming an active structure material layer co...
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WO/2024/089570A1 |
Provided is a new semiconductor device. This semiconductor device has: a memory cell circuit having a first transistor and a capacitive element; and a read-out circuit having a second transistor and a third transistor. An element layer i...
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WO/2024/087955A1 |
A semiconductor device and a manufacturing method therefor, the semiconductor device comprising: a substrate (1); a semiconductor layer (2) provided on the substrate (1) and comprising a first semiconductor lamination layer and a second ...
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WO/2024/092176A1 |
An enhanced edge termination structure for use in a charge balanced semiconductor device is provided. The edge termination structure includes a plurality of edge termination trenches and a plurality of semiconductor mesa regions, each of...
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WO/2024/087189A1 |
Disclosed in the present application are an anti-radiation field effect transistor device and application thereof in an anti-radiation environment, which are used for solving the problem in the prior art of an anti-radiation method for a...
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WO/2024/091302A1 |
A semiconductor structure includes a stack of alternating doped semiconductor epitaxial layers and cap epitaxial layers formed on a substrate. Each doped semiconductor epitaxial layer includes silicon having carrier dopants, and each cap...
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WO/2024/087713A1 |
A display panel and a display device. The display panel further comprises a substrate (10), a shielding layer (20), and a driving circuit layer (30); the shielding layer (20) is arranged on the substrate (10); the driving circuit layer (...
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WO/2024/091487A1 |
Disclosed is a technique for transporting and arranging electronic components, using an optical system utilizing a laser beam to produce an optical trap in a fluid near a target site of a backplate, where a primary optical axis of the la...
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WO/2024/091422A1 |
A three-dimensional (3D) dynamic random-access memory (DRAM) includes a substrate and a plurality of nanosheet transistors stacked vertically on a surface of the substrate. Each of the nanosheet transistors comprises a gate, a source, an...
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WO/2024/087188A1 |
Disclosed in the present application is a field effect transistor device having a blocking region, which device is used for alleviating the problem in the prior art of a short-channel effect of a field effect transistor. The field effect...
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WO/2024/090370A1 |
According to the present disclosure, it is possible to achieve a magnetic domain wall moving element capable of improving a magnetic domain wall moving speed. A magnetic domain wall moving element according to one embodiment of the prese...
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WO/2024/090117A1 |
A semiconductor substrate (11) comprises an FS layer (13) between a collector layer (12) and a drift layer (14). A total dose amount of the collector layer (12) is less than 1×1013/cm2. The collector layer (12) has a plurality of peaks ...
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WO/2024/090243A1 |
A semiconductor device (1) is provided with, in plan view: a transistor (10) formed in a first region (A1) of a semiconductor layer (40); a transistor (20) formed in a second region (A2) adjacent to the first region (A1) of the semicondu...
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WO/2024/092179A1 |
A semiconductor device is provided that includes an epitaxial layer disposed on a semiconductor substrate, the epitaxial layer including an active region, in which at least one active element is formed, and an edge termination region, in...
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WO/2024/087703A1 |
Provided in the present application are a transistor, an integrated circuit and a preparation method, and an electronic device. The transistor comprises a channel and a gate arranged on the channel. The gate comprises a coverage layer ar...
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WO/2024/087634A1 |
The present application relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: an isolation tray (118) having a first conductivity type; an injection assistance structure comprisi...
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WO/2024/090081A1 |
[Problem] To provide an amplifier circuit, a comparator, and a solid-state imaging device that can suppress RTS noise. [Solution] An amplifier circuit according to the present disclosure comprises: an active load; and a plurality of inpu...
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WO/2024/089571A1 |
Provided is a semiconductor device having favorable electrical properties. This semiconductor device has a transistor, a first interlayer insulating layer, and a second interlayer insulating layer on the first interlayer insulating layer...
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WO/2024/085097A1 |
[Problem] When a magnetic field detection element is formed on an Si substrate, reducing the coil pitch inside an inverted-trapezoidal groove makes it easier for the step at an upper part of the groove or the edge of a bottom surface of ...
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WO/2024/085528A1 |
The present invention relates to a thin-film transistor and a manufacturing method therefor. The thin film transistor comprises: a gate electrode; an active layer spaced apart from the gate electrode; a source electrode provided on one s...
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WO/2024/086458A1 |
A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each ga...
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WO/2024/084621A1 |
In the present invention, an epitaxial layer (2) is formed on a substrate (1). A field effect transistor (3) is formed on the epitaxial layer (2). A drain pad (8) is formed on the epitaxial layer (2). The drain pad (8) is connected to a ...
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WO/2024/086064A1 |
Semiconductor devices and methods of manufacturing the same are described. The method includes forming a source region and a drain region adjacent a superlattice structure on a substrate. The source region and the drain region comprise a...
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WO/2024/082395A1 |
A transistor, a 3D memory and a manufacturing method therefor, and an electronic device, relating to the technical field of semiconductors. The 3D memory comprises multiple layers of memory cells stacked in a direction perpendicular to a...
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WO/2024/084366A1 |
Provided is a semiconductor device that enables miniaturization or higher integration. Provided is an oxide semiconductor suitable for the semiconductor device. Formed is an oxide semiconductor that has a small difference in thickness be...
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WO/2024/084778A1 |
The present invention achieves a high withstand voltage by means of an outer peripheral region having a small width. A semiconductor device according to the present invention comprises: a semiconductor substrate that has an element regio...
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WO/2024/082655A1 |
Provided in the embodiments of the present application are a high electron mobility transistor device and a manufacturing method therefor. The device (100) has a structural unit (10) or at least two structural units (10), which are repea...
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WO/2024/086220A1 |
A metal-oxide-semiconductor (MOS) capacitor can include a substrate comprising a semiconductor material, an oxide layer formed over a first surface of the substrate, a resistive layer formed over at least a portion of the oxide layer, an...
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WO/2024/084910A1 |
According to the present invention, a first main surface has a central measurement region, a first measurement region, a second measurement region, a third measurement region, and a fourth measurement region. When viewed along a straight...
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WO/2024/086163A1 |
N-polar HEMT structures and methods of forming HEMT structures. An example semiconductor device includes a III-N material structure, comprising: a III-N backbarrier layer; a III-N channel layer over an N-face of the III-N backbarrier lay...
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WO/2024/084833A1 |
For example, a semiconductor device 1 includes a semiconductor substrate (N-SUB) of a first conductivity type, a well (P/W) of a second conductivity type different from the first conductivity type that is formed in the semiconductor subs...
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WO/2024/083312A1 |
The disclosure relates to a power MOSFET device (10) having a source terminal, a drain terminal and a gate terminal. The power MOSFET device comprises a drain contact (105) formed at a bottom side (11) of the MOSFET device; a first elect...
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WO/2024/083028A1 |
Provided in the embodiments of the present application is a semiconductor super-junction power device, comprising: an n-type semiconductor layer (21); a plurality of columnar insulating layers (22) recessed in the n-type semiconductor la...
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WO/2024/084438A1 |
A nonvolatile flash memory cell (300) includes a source electrode (306), a drain electrode (308), and a gate column (310). The drain electrode (308) is cylindrical, the gate column (310) is tubular and surrounds the drain electrode (308)...
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WO/2024/082636A1 |
The present invention provides a Schottky barrier diode, comprising: an ohmic electrode layer 4; a second semiconductor layer 32, wherein the lower surface of the second semiconductor layer 32 forms an ohmic contact with the upper surfac...
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WO/2024/086539A1 |
A three-terminal bidirectional GaN FET with a single gate. The device is formed by integrating a single-gate bidirectional GaN FET in parallel with a bidirectional device formed of two back-to-back GaN FETs having a source without a pin-...
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WO/2024/082422A1 |
A method for forming a buried bit line, a memory and a manufacturing method therefor, and an electronic device. The memory comprises a plurality of transistors, and further comprises: a first dielectric layer (41), a second dielectric la...
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WO/2024/084905A1 |
This nitride semiconductor device (10) is provided with: a first nitride semiconductor layer (16); a second nitride semiconductor layer (18) which is formed on the first nitride semiconductor layer (16), and has a larger band gap than th...
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WO/2024/082734A1 |
A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located o...
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WO/2024/084652A1 |
A field-effect transistor according to the present invention comprises: a gate (13) formed from a plurality of intersecting electrode wires; a plurality of source electrodes (11); a plurality of drain electrodes (12); and a feed section ...
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WO/2024/083108A1 |
The present application provides an electronic device and a manufacturing method therefor. The electronic device comprises a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first conductive structu...
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WO/2024/078043A1 |
A display panel, which comprises: a substrate, a multi-layer ohmic contact layer, a multi-layer insulating layer, a semiconductor layer, a gate electrode and a source/drain electrode layer; at least one insulating layer is arranged betwe...
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WO/2024/081401A1 |
A method of forming a semiconductor structure includes forming an epitaxial semiconductor island having a first material characteristic on a base layer, and growing an epitaxial structure from the epitaxial semiconductor island and the b...
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