TECHNICAL FIELD

The disclosure relates to the field of Silicon Technology for power device applications. In particular, the disclosure relates to a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device and a method for manufacturing a power MOSFET device.

BACKGROUND

Silicon Trench Power MOSFETs have become an industry standard since more than three decades and they have replaced their planar counterparts thanks to their superior performance and large benefits in all possible industrial application of interest. The main advantages of Trench Silicon Power MOSFET can be schematically summarized as follows: combined high- efficiency and fast switching; reduced gate charge; improved Drain-Source ON-resistance and device current capability; and reduced switching losses.

Historically, each generation of trench power MOSFET has achieved a lower specific ON- resistance by reducing its cell dimensions and by increasing its cell density. In higher switching speed applications, a fundamental challenge to increase the cell density comes from the direct correlation between the higher cell density and the correspondent higher gate-to-drain feedback capacitance CGD. In low voltage power circuits, this Miller capacitance plays a fundamental role in determining the overall device performance and also strongly affects its stability. Indeed, under certain operations such as half-bridge configuration an excessively high gate-to-drain capacitance CGD can cause the so-called “spurious turn-on” where the supposedly off-state biased power MOSFET can suffer from unwanted accidental re-turn-on effects. If that happens, the contemporary conductions, even for very short time, of both the high-side and the low-side transistors can compromise the overall circuit performance, its stability and controllability and, finally, can also strongly compromise the power MOSFETs reliability due to uncontrolled voltage and/or current spikes.

SUMMARY

This disclosure provides a solution for overcoming limitations in device performance and stability as described above.

In particular, the disclosure provides a solution for reducing the Miller effect and the gate-to- drain capacitance, without affecting nor compromising the other device properties. The foregoing and other objectives are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

In this disclosure, a new device design is presented that combines the advantages of a sidegate technology with the advantages of a split-gate technology as presented below.

The side-gate technology is a design where the power MOSFET device can be effectively manufactured by producing a deep trench which is filled with a metal electrode that is connected to the source terminal and next to it a smaller trench can be formed and filled with a metal electrode that is connected to the gate terminal. The main advantage of this design is represented by a reduced manufacturing process complexity. In particular, the lack of the inter- poly dielectric layer (IPO), i.e., the dielectric layer that is formed between the top-side gate electrode and the source electrode, largely simplifies the manufacturing process of this device and allows to reduce costs and a better control of the technology.

The split-gate technology is a design where a source connected field plate electrode is separated from the top side gate electrode. The main advantage of this design is that the presence of the source connected field plate electrode effectively decouples the gate electrode from the drain contact and a strong reduction in the CGD can be consequently observed. This provides the advantage of reducing the Miller contributions and thus improved reliability and stability of the power MOSFET device.

A novel vertical power MOSFET is presented that possesses multiple-field plates allowing optimization of the overall performance of the device in a unique manner. A trench Si MOSFET with multi-graded field plate is described.

The main advantages of the novel power MOSFET design can be summarized as follows: 1) Largely reduced gate-to-drain capacitance thanks to the decoupling effects of the second source field plated placed underneath the gate electrode. 2) Slanted-like field plated design is used to improve the overall breakdown capability of this design. Indeed, two different dielectric thicknesses (see 122 and 125 in Figure 1) can be independently tuned to achieve optimal device performance. 3) Improved robustness against spurious turn-on effects thanks to the improved QGD/QGS ratio. 4) Higher degree of freedom in tailoring the device performance thanks to the higher number of parameters that can be independently selected or adjusted: Parameters 121 , 122, 123, 124, 125, 126, (see Figure 1), doping, pitch, trench depth, etc. 5) Possibility to connect the additional field plate below the gate electrode to different voltage, if needed. A floating field plate configuration is also possible.

In this disclosure, MOSFET devices, in particular power MOSFET devices are described. The Metal Oxide Semiconductor Field Effect T ransistor (MOSFET) is a type of field-effect transistor (FET), fabricated by the controlled oxidation of silicon. It has an insulated gate, the voltage of which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. A power MOSFET is a specific type of MOSFET designed to handle significant power levels. The power MOSFET is the most common power semiconductor device in the world, due to its low gate drive power, fast switching speed, easy advanced paralleling capability, wide bandwidth, ruggedness, easy drive, simple biasing, ease of application, and ease of repair. It can be used in a wide range of applications, such as most power supplies, DC-to-DC converters, motor controllers and many other applications.

Embodiments of the disclosure provide novel power MOSFET devices with improved reliability and stability. These novel power MOSFET devices provide improved performance by a design reducing the Miller effect and the gate-to-drain capacitance, without significantly affecting nor compromising the other device properties.

According to a first aspect, the disclosure relates to a power Metal Oxide Semiconductor Field Effect Transistor, MOSFET, device having a source terminal, a drain terminal and a gate terminal, the power MOSFET device comprising: a drain contact formed at a bottom side of the MOSFET device, the drain contact being electrically connected to the drain terminal; a first electrode formed at a top side of the MOSFET device, the top side opposing the bottom side, the first electrode being electrically connected to the gate terminal; a second electrode formed at the top side of the MOSFET device, the second electrode being spaced apart from the first electrode, the second electrode being electrically connected to the source terminal; and a third electrode formed between the first electrode and the drain contact, the third electrode being spaced apart from the first electrode, the third electrode being electrically connected to the source terminal, wherein the third electrode is configured to reduce a capacitive coupling of the first electrode to the drain contact.

In this design of the power MOSFET device, the third electrode, which can be a source connected field plate electrode, is separated from the first electrode (e.g., gate electrode). The main advantage of such a design is that the presence of the third electrode effectively decouples the first electrode (e.g., gate electrode) from the second electrode (e.g., source electrode) and a strong reduction in the CGD can be consequently observed. This provides the advantage of reducing the Miller contributions and thus improved reliability and stability of the power MOSFET device.

Hence, such a power MOSFET device provides the advantage of largely reduced gate-to-drain capacitance thanks to the decoupling effects of the third electrode (e.g., Source) placed underneath the first electrode (e.g., Gate). The overall breakdown capability and robustness against spurious turn-on effects are improved by this third electrode design.

The power MOSFET device can be a vertical device, for example, a device in which the current flow is in a vertical direction, i.e., from the top side (Source) to the bottom side (drain) of the device. A lateral direction can be defined as a direction along the top side or bottom side, i.e., orthogonal to the vertical direction of the device.

In an exemplary implementation of the power MOSFET device, the third electrode is spaced apart from the second electrode. Accordingly, the size of the third electrode (e.g., source) can be adapted to the size of the first electrode (e.g., gate) for a better decoupling of the gate electrode from the drain contact and thus reduction of the capacitance between gate and drain.

In an exemplary implementation of the power MOSFET device, the third electrode and the second electrode are electrically connected, forming a T-shaped plate. Such a design provides that both electrodes can be manufactured more easily, e.g., by using a single process step for producing both electrodes.

The T-shape does not have to be symmetrical, i.e., the base bar of the T does not have to connect the upper bar of the T in the middle point of the upper bar, it can also be left or right to the middle point or even at a lower end of the upper bar.

In an exemplary implementation of the power MOSFET device, the third electrode is formed below the first electrode and lateral to the second electrode. Thus, the third electrode can efficiently decouple the first electrode from the drain contact, thereby reducing the CGD capacitance.

In an exemplary implementation of the power MOSFET device, the first electrode is arranged laterally offset from the third electrode. The gate electrode can be formed closer to the channel region which results in a better controllability of the power MOSFET device by the voltage applied to the gate electrode. In an exemplary implementation of the power MOSFET device, the power MOSFET device comprises: a drift region formed above the drain contact; and a trench filled with dielectric material, the trench being formed in the drift region, wherein the first electrode, the second electrode and the third electrode are formed in the trench. This trench design provides the following advantages: high-efficiency and fast switching transistor device, reduced gate charge, improved RDS on resistance, improved device current capability and reduced switching losses.

Besides the above advantages, the power MOSFET device also provides significant advantages for manufacturing. The power MOSFET device can be effectively manufactured by producing a deep trench which is filled with a metal electrode (the second electrode) that is connected to the source terminal and next to it a smaller trench can be formed and filled with a metal electrode (the first electrode) that is connected to the gate terminal. This design, also referred to as “side-gate technology”, is represented by the reduced manufacturing process complexity. In particular, the lack of the inter-poly dielectric layer (IPO), i.e. , the dielectric layer that is formed between the top-side gate electrode and the source electrode, largely simplifies the manufacturing process of the device and allows to reduce costs and a better control of the technology.

In an exemplary implementation of the power MOSFET device, the trench has a bottom side and a top side opposing the bottom side, wherein the top side of the trench corresponds to the top side of the MOSFET device, wherein the trench has at least one sidewall between the bottom side and the top side of the trench. Such a power MOSFET device can be flexible designed in order to meet requirements with respect to stability, reliability, controllability and overall circuit performance.

The sidewall is a lateral boundary of the trench that defines together with the top side and the bottom side the geometrical shape of the trench. This geometrical shape can be a box shaped container or any other 3-dimensional container form. For example, the bottom side as well as the side wall can be even or inclined. The top side of the trench is typically even.

In an exemplary implementation of the power MOSFET device, a vertical extension of the third electrode is less than a vertical extension of the second electrode. Thus, the third electrode can be used as a source-connected field plate between the gate electrode and the drain contact in order to reduce the gate-to-drain capacitance and thus to improve robustness against spurious tun-on effects. In an exemplary implementation of the power MOSFET device, a lateral extension of the third electrode corresponds to a lateral extension of the second electrode and/or to a lateral extension of the first electrode. Therefore, the electrodes can be efficiently manufactured, e.g., by using the same process masks.

The lateral extension specifies an extension along the top side or bottom side of the device or a parallel plane thereof, while the vertical extension specifies an extension from the top side to the bottom side of the device.

In an exemplary implementation of the power MOSFET device, a distance of the second electrode from the bottom side of the trench is less than a distance of the third electrode from the bottom side of the trench. This provides a higher degree of tailoring the device due to the different parameters, e.g. the two distances can be selected/optimized independently.

In an exemplary implementation of the power MOSFET device, a thickness of the dielectric material in the trench between the second electrode and the at least one sidewall of the trench is less or equal than a thickness of the dielectric material in the trench between the second electrode and the bottom side of the trench. By increasing the dielectric thickness to the bottom of the trench, while leaving a thinner dielectric thickness at the sidewall of the trench improves the electric field shaping effect of the field plate, e.g. the third electrode. The main effect of the thicker bottom oxide dielectric is to introduce a larger physical separation between the gate electrode and the bottom side drain contact. This, in turn, induces a reduction of the gate-to- drain capacitance.

In an exemplary implementation of the power MOSFET device, a thickness of the dielectric material in the trench between the first electrode and the at least one sidewall of the trench is less than a thickness of the dielectric material in the trench between the third electrode and the at least one sidewall of the trench. Thus, a higher degree of freedom for selecting/optimizing device parameters and performance depending on the specific application is provided.

In an exemplary implementation of the power MOSFET device, a relation of the thickness of the dielectric material in the trench between the third electrode and the at least one sidewall of the trench to a thickness of the dielectric material in the trench between the second electrode and the at least one sidewall of the trench corresponds to a predefined characteristic. Therefore, improved robustness against spurious turn-on effects is provided. In an exemplary implementation of the power MOSFET device, the power MOSFET device comprises: a source contact formed in the drift region at the top side of the MOSFET device adjacent to the trench; and a channel region formed in the drift region below the source contact and lateral to the first electrode, wherein the channel region is configured to enable a current flow between the source contact and the drain contact via the drift region based on a voltage of the first electrode leading to improved controllability and reliability of the power MOSFET device.

In an exemplary implementation of the power MOSFET device, the drift region is formed as an n-type doped silicon region; and the channel region is formed as a p-type doped region. This provides the advantage of an easy manufacturing of the device.

In an exemplary implementation of the power MOSFET device, the second electrode and the third electrode are connected to different voltages. Thus, an independent control of the third electrode and the second electrode is provided. A floating field plate configuration can also be realized.

In an exemplary implementation of the power MOSFET device, the first electrode, the second electrode and the third electrode are made of a conductive material comprising a metal and/or a Polysilicon. This provides the advantage of flexibility in material choice.

In an exemplary implementation of the power MOSFET device, the second electrode and the third electrode are made of different conductive materials.

According to a second aspect, the disclosure relates to a method for producing a power Metal Oxide Semiconductor Field Effect Transistor, MOSFET, device, the method comprising: forming a drift region in an epitaxial layer on a substrate; forming a drain contact at a bottom side of the substrate, and electrically connecting the drain contact to a drain terminal; forming a trench in the drift region and filling the trench with dielectric material; forming a first electrode extending from a top side of the trench into the trench, the top side of the trench opposing the bottom side of the substrate, and electrically connecting the first electrode to a gate terminal; forming a second electrode extending from the top side of the trench into the trench, the second electrode being spaced apart from the first electrode, and electrically connecting the second electrode to a source terminal; and forming a third electrode in the trench between the first electrode and the drain contact, the third electrode being spaced apart from the first electrode, and electrically connecting the third electrode to the source terminal. Such a method provides the advantage of easy and efficient manufacturing a power MOSFET device having largely reduced gate-to-drain capacitance thanks to the decoupling effects of the third electrode (e.g., Source) placed underneath the first electrode (e.g., Gate). A power MOSFET device can be manufactured having overall breakdown capability and robustness against spurious turn-on effects.

The advantages of the methods according to the second aspect are the same as those for the corresponding implementation forms of the first apparatus according to the first aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the disclosure will be described with respect to the following figures, in which:

Figure 1 shows a schematic cross section of a power MOSFET device 10 according to a first embodiment;

Figure 2 shows a schematic cross section of a power MOSFET device 20 according to a second embodiment;

Figure 3a shows a schematic cross section of a power MOSFET device 30 according to a third embodiment;

Figure 3b shows a representation of a larger cross section of the power MOSFET device 30 shown in Figure 3a;

Figure 3c shows a schematic top view of the power MOSFET device 30 shown in Figure 3a;

Figure 4 shows a schematic process flow for manufacturing a power MOSFET device according to the disclosure; and

Figures 5a, 5b and 5c show performance diagrams 500a, 500b, 500c of a power MOSFET device according to the disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

Figure 1 shows a schematic cross section of a power MOSFET device 10 according to a first embodiment.

The power MOSFET device 10 includes a source terminal, a drain terminal and a gate terminal (not shown in Figure 1).

The power MOSFET device 10 comprises a drain contact 105 formed at a bottom side 11 of the MOSFET device 10. The drain contact 105 is electrically connected to the drain terminal.

The power MOSFET device 10 comprises a first electrode 103, e.g., a gate electrode (G), formed at a top side 12 of the MOSFET device 10. The top side 12 is opposing the bottom side 11 . The first electrode 103 is electrically connected to the gate terminal.

The power MOSFET device 10 comprises a second electrode 102a, e.g., a source electrode (S), formed at the top side 12 of the MOSFET device 10. The second electrode 102a is spaced apart 127 from the first electrode 103. The second electrode 102a is electrically connected to the source terminal.

The power MOSFET device 10 comprises a third electrode 102b, e.g., a source field plate (S), formed between the first electrode 103 and the drain contact 105. The third electrode 102b is spaced apart 123 from the first electrode 103. The third electrode 102b can be electrically connected to the source terminal.

However, the third electrode 102b can also be connected to a different voltage terminal. For example, the third electrode 102b can be connected to the gate contact or to the source contact, e.g., depending on the working principle to be implemented.

The third electrode 102b is configured to reduce a capacitive coupling of the first electrode 103 to the drain contact 105.

Such a power MOSFET device 10 provides the advantage of largely reduced gate-to-drain capacitance thanks to the decoupling effects of the third electrode 102b (Source) placed underneath the first electrode 103 (Gate). The overall breakdown capability and robustness against spurious turn-on effects are improved by this third electrode 102b design.

The power MOSFET device can be a vertical device, for example, a device in which the current flow is in a vertical direction, i.e., from the top side (Source) to the bottom side (drain) of the device. A lateral direction can be defined as a direction along the top side or bottom side, i.e., orthogonal to the vertical direction of the device.

In the first embodiment shown in Figure 1 , the third electrode 102b is spaced apart 128 from the second electrode 102a. This is different from the second embodiment shown in Figure 2, where the third electrode 102b and the second electrode 102a are electrically connected, e.g., forming a T-shaped plate.

The third electrode 102b of the power MOSFET device 10 may be formed below the first electrode 103 and lateral to the second electrode 102a as shown in Figure 1.

In particular, the first electrode 103 may be arranged laterally offset 121 , 122 from the third electrode 102b, as can be seen from Figure 1. That means, the third electrode 102b is not aligned with the first electrode 103 in vertical direction (from top to bottom in Figure 1) but an offset is applied in horizontal direction (from left to right in Figure 1). In Figure 1 , an offset to the right is applied to the first electrode 103 in relation to the third electrode 102b. It understands that in another embodiment, an offset to the left can be applied as well.

The power MOSFET device 10 comprises a drift region 100 formed above the drain contact 105; and a trench 101 filled with dielectric material. The trench 101 is formed in the drift region 100. The first electrode 103, the second electrode 102a and the third electrode 102b are formed in the trench 101 as can be seen from Figure 1.

When manufacturing this power MOSFET device 10, a first trench can be manufactured, the second electrode 102a can be manufactured in the first trench and the first trench can be filled with dielectric material. Then, a second trench can be manufactured for forming the third electrode 102b and the first electrode 103 and the second trench can be filled with dielectric material, e.g., as described below with respect to Figure 4. However, in the final product, no two trenches can be identified, but only one trench 101 which is filled with dielectric material, and which includes the first electrode 103, the second electrode 102a and the third electrode Nevertheless, manufacturing the power MOSFET device 10 is easy to perform.

As can be seen from Figure 1 , the trench 101 has a bottom side 13 and a top side 12 opposing the bottom side 13. The top side 12 of the trench 101 may correspond to the top side 12 of the MOSFET device 10 as shown in Figure 1. The trench 101 has at least one sidewall 14 (or side face) between the bottom side 13 and the top side 12 of the trench 101.

The sidewall 14 is a lateral boundary of the trench 101 that defines together with the top side 12 and the bottom side 13 the geometrical shape of the trench 101. This geometrical shape can be a box shaped container or any other 3-dimensional container form. For example, the bottom side 13 can be even or inclined and so also the sidewall 14 can be even or inclined. The top side 12 of the trench 101 is typically even.

As shown in Figure 1 , a vertical extension 124 (from top side 12 to bottom side 13 shown in Figure 1) of the third electrode 102b may be less than a vertical extension 129 of the second electrode 102a.

A lateral extension (from left side to right side shown in Figure 1) of the third electrode 102b may correspond to a lateral extension of the second electrode 102a and/or to a lateral extension of the first electrode 103.

A distance 126 of the second electrode 102a from the bottom side 13 of the trench 101 may be less than a distance 130 of the third electrode 102b from the bottom side 13 of the trench 101 , as can be seen from Figure 1.

A thickness 125 of the dielectric material in the trench 101 between the second electrode 102a and the at least one sidewall 14 of the trench 101 , as shown in Figure 1 , can be less or equal than a thickness 126 of the dielectric material in the trench 101 between the second electrode 102a and the bottom side 13 of the trench 101.

A thickness 121 of the dielectric material in the trench 101 between the first electrode 103 and the at least one sidewall 14 of the trench 101 may be less than a thickness 122 of the dielectric material in the trench 101 between the third electrode 102b and the at least one sidewall 14 of the trench 101.

The horizontal offset of the first electrode 103 with respect to the third electrode 102b depends on those thicknesses 121 and 122. A relation of the thickness 122 of the dielectric material in the trench 101 between the third electrode 102b and the at least one sidewall 14 of the trench 101 to a thickness 125 of the dielectric material in the trench 101 between the second electrode 102a and the at least one sidewall 14 of the trench 101 may correspond to a predefined characteristic. That means, the power MOSFET device 10 can be designed according to this relation in order to guarantee specific properties, such as stability, reliability, etc.

The power MOSFET device 10 may further comprise: a source contact 106 formed in the drift region 100 at the top side 12 of the MOSFET device 10 adjacent to the trench 101 ; and a channel region 104 (e.g., p-body) formed in the drift region 100 below the source contact 106 and lateral to the first electrode 103. The channel region 104 is configured to enable a current flow between the source contact 106 and the drain contact 105 via the drift region 100 based on a voltage of the first electrode 103, e.g., a voltage applied to the gate electrode.

As shown in Figure 1 , the drift region 100 may be formed as an n-type doped silicon region; and the channel region 104 may be formed as a p-type doped region.

In the embodiment shown in Figure 1 , where the second electrode 102a and the third electrode 102b are spaced apart from each other, the second electrode 102a and the third electrode 102b may be connected to different voltages.

The first electrode 103, the second electrode 102a and the third electrode 102b may be made of a conductive material, e.g., made of metal, a metal alloy or Polysilicon or any combination thereof.

In one exemplary embodiment, the second electrode 102a and the third electrode 102b may be made of different conductive materials or of different combinations of conductive materials.

In the following, an exemplary implementation of the power MOSFET device 10 is described in more detail. The power MOSFET device 10 is a trench power MOSFET, where a trench 101 is formed in an n-type silicon region 100 and subsequently filled with dielectric material. In the very same trench, three different metal electrodes 102a, 102b, 103 are formed. One metal electrode 103 is connected to the gate terminal and it is enclosed by two additional metal electrodes 102a, 102b connected both to the source terminal. The device comprises also a p- type region that defines the overall channel length 104. Top side source contact 106 and bottom side drain contact 105 are also formed. A trench 101 of a certain depth is formed and filled, afterwards, with a dielectric and with a gate metal electrode 103 and two additional metal electrodes 102a, 102b connected both to the source terminal. A p-type implant is used to form the channel region 104 and it will effectively determine the device channel length. Finally, the source top n+ region 106 is implanted. With a positive voltage applied to the gate electrode 103, an electron inversion channel will form at the interface between the silicon channel and the dielectric interface. Once the inversion layer is formed, the current can flow vertically from the n+ top source contact 106, through the p-type inverted channel 104, through the n-type drift region 100 and it will be finally collected by the bottom side n+ drain electrode 105. The trench depth, the dielectric thickness and the doping profile in the channel and drift region, can be all optimized at the same time, in order to achieve the aforementioned superior performance.

While Figure 1 shows only one source connected field plate, e.g. the third electrode 102b, it understands that multiple of such field plates 102b may be implemented, in order to improve design flexibility and obtain higher degree of freedom in tailoring the device performance.

Figure 2 shows a schematic cross section of a power MOSFET device 20 according to a second embodiment.

In this second embodiment, the power MOSFET device 20 may correspond to the power MOSFET device 10 of the first embodiment described above, but there is no gap between the second electrode 102a and the third electrode 102b. Both electrodes 102a, 102b are in contact with each other and electrically connected.

The third electrode 102b and the second electrode 102a are electrically connected, e.g., forming a T-shaped plate.

The T-shape does not have to be symmetrical, i.e., the base bar of the T does not have to connect the upper bar of the T in the middle point of the upper bar, it can also be left or right to the middle point or even at a lower end of the upper bar.

In Figure 2, no symmetrical T-shape is shown, instead an asymmetric T-shape with respect to the connection area of the second electrode 102a and the third electrode 102b is illustrated.

Instead of a T-shape the second electrode 102a and the third electrode 102b may also be connected in an L-shape. The power MOSFET device 20 may have the same features as described above with respect to Figure 1. However, due to the electrical connection of the second electrode 102a and the third electrode 102b, both electrodes are at the same electrical potential and connected to the same voltage.

Figure 3a shows a schematic cross section of a power MOSFET device 30 according to a third embodiment.

In this third embodiment, the power MOSFET device 30 may correspond to the power MOSFET device 10 of the first embodiment described above. As in the first embodiment, also in this third embodiment, there is a gap between the second electrode 102a and the third electrode 102b.

The power MOSFET device 30 may have the same features as described above with respect to Figure 1. However, the trench 101 in Figure 1 is only a schematical representation while Figure 3a shows a more realistic representation of the trench 101. In particular, the trench 101 does not have to be formed in strict horizontal and vertical direction and in straight lines as shown in Figure 1. It can be rather formed having rounded edges as well as a round bottom and round side walls, e.g., in a parabolic shape as illustrated in Figure 3a.

In one exemplary composition, the first electrode 103, the second electrode 102a and the third electrode 102b may be made of Polysilicon 202. The drift region 100 may be made of Silicon 203, the top side metal contact may be made of Aluminum 201 and the dielectric material of the trench 101 may be SiO2, 204.

Figure 3b shows a representation of a larger cross section of the power MOSFET device 30 shown in Figure 3a. In this larger cross section, it can be seen, that multiple trenches 101 are arranged laterally with respect to each other (e.g. from left side to right side of Figure 3b) in the drift region 100.

In each trench 101 a pair of first electrodes 103 and third electrodes 102b is arranged symmetrically about the second electrode 102a. For example, one first electrode 103 and one third electrode 102b are placed at the left side of the trench 101 (not shown in Figure 3a) and another first electrode 103 and another third electrode 102b are placed at the right side of the trench 101 as shown in Figure 3a. Figure 3c shows a schematic top view of the power MOSFET device 30 shown in Figure 3a.

The top view shows multiple unit cells with active area 310 below which a respective trench 101 with electrodes 103, 102a, 102b is arranged and edge termination 311 surrounding the active area 310.

In this exemplary implementation of the power MOSFET device 30, the gate pad 303 forming the gate terminal may be placed in one corner of the active area 310.

Figure 4 shows a schematic process flow for manufacturing a power MOSFET device according to the disclosure.

The main process steps can be summarized as follows:

1 . Forming an epitaxial (epi) layer on substrate 401 : Starting with the epitaxial layer, multi- step doping in the starting epi layer can also be implemented for better device performance. This epitaxial layer may represent the drift layer 100 described above with respect to Figures 1 to 3.

2. Active Trench Formation 402. The trench 101 as illustrated in Figures 1 to 3 may be formed in this step.

3. Deposit thick dielectric layer 403: The trench is filled with a thick dielectric layer. The thick dielectric layer means that the dielectric layer fills the trench 101 as described above with respect to Figures 1 to 3.

4. Deposit conductive material 404 into the trench for source electrode formation, i.e., source field plate formation. This source electrode may correspond to the second electrode 102a as described above with respect to Figures 1 to 3.

5. Planarization step 405: form planarized surface. The top side 12 of the trench 101 shown in Figures 1 , 2, 3 can be formed having a planarized surface.

6. Partial removal of thick dielectric layer 406: In this production step, a second trench may be formed to accommodate the first and third electrodes 103, 102b as described above with respect to Figures 1 to 3. This second trench is not shown in Figures 1 , 2 and 3.

7. Thin layer dielectric deposition 407 for field oxide layer.

8. Source field plate formation 408: The third electrode 102b, as described above with respect to Figures 1 to 3, may be formed as a source field plate.

9. Dielectric layer deposition to form IPO (inter-poly oxide) 409.

10. Partial removal of dielectric layer from sidewall 410.

11. Gate dielectric formation 411. 12. deposit dielectric material into trench to form gate electrode 412. The gate electrode may correspond to the first electrode 103 as described above with respect to Figures 1 to 3.

13. P-type implantation forming p-body 413. The p-body may represent the channel region 104 as described above with respect to Figures 1 to 3.

14. N-type implantation forming source contact 414. The source contact may correspond to the source contact 106 as described above with respect to Figures 1 to 3.

15. ILD (inter layer dielectric) layer deposition 415.

16. Contact formation 416. The drain contact 105 as described above with respect to Figures 1 to 3 may be formed.

In the following, a method is described that may use the above-described process steps for producing a power MOSFET device, e.g., a power MOSFET device 10, 20, 30 as described above with respect to Figures 1 to 3.

The method comprises: forming a drift region 100 in an epitaxial layer on a substrate. This may be implemented by process step 1 as described above.

The method comprises: forming a drain contact 105 at a bottom side 11 of the substrate, and electrically connecting the drain contact 105 to a drain terminal. This may be implemented by process step 16 as described above.

The method comprises: forming a trench 101 in the drift region 100 and filling the trench 101 with dielectric material. This may be implemented by process steps 2 and 3 as described above.

The method comprises: forming a first electrode 103 extending from a top side 12 of the trench 101 into the trench 101 , the top side 12 of the trench 101 opposing the bottom side 11 of the substrate, and electrically connecting the first electrode 103 to a gate terminal. This may be implemented by process step 12 as described above.

The method comprises: forming a second electrode 102a extending from the top side of the trench 101 into the trench 101 , the second electrode 102a being spaced apart 127 from the first electrode 103, and electrically connecting the second electrode 102a to a source terminal. This may be implemented by process step 4 as described above.

The method comprises: forming a third electrode 102b in the trench 101 between the first electrode 103 and the drain contact 105, the third electrode 102b being spaced apart 123 from the first electrode 103, and electrically connecting the third electrode 102b to the source terminal. This may be implemented by process step 8 as described above.

One or more of the other production steps described above may be required to manufacture the power MOSFET device by the above-described method.

Figures 5a, 5b and 5c show performance diagrams 500a, 500b, 500c of a power MOSFET device according to the disclosure.

The performance of the disclosed power MOSFET device described above with respect to Figures 1 to 3 has been simulated by means of process and device calibrated simulations. In the 2D simulation results of the design of a multi-field plate vertical power MOSFET, a rated voltage class of 150V has been considered. The potential distribution, the electric field profile and the impact ionization profile show superior performance.

The device geometry and the different geometry (parameters 121 , 122, 123, 124, 125, 126 as shown in Figure 1 , for example) have been optimized with respect to breakdown capability and on-state resistance.

Figure 5a shows the simulated breakdown voltage 502 of the novel power MOSFET device, compared with a reference 150V MOSFET device 501 which is based only on the side-gate design. As visible in the figure, the novel design 502 allows to achieve the same breakdown strength (or even higher) of the reference device 501.

Figure 5b shows the simulated C-V curves of the novel power MOSFET device and of the reference device. The three main relevant capacitances have been simulated, which are the input capacitance Ciss, the output capacitance Coss and the reverse transfer capacitance Crss.

In particular, curve 503 shows input capacitance Ciss of the novel power MOSFET device; curve 504 shows input capacitance Ciss of the reference device; curve 505 shows output capacitance Coss of the reference device; curve 506 shows output capacitance Coss of the novel power MOSFET device; curve 507 shows reverse transfer capacitance Crss of the reference device; and curve 508 shows reverse transfer capacitance Crss of the novel power MOSFET device. It is possible to observe three main aspects:

1) Very large reduction in the gate-to-drain capacitance CGD compared to the reference device.

2) Same output capacitance Coss.

3) Small increase in the input capacitance Ciss compared to the reference device.

The largely reduced gate-to-drain capacitance will allow a massive improvement in the overall converter efficiency (DC-DC converter). Moreover, the reduced CGD and the slightly increased CGS will allow the device to be much more robust against unwanted spurious turn-on effects.

Figure 5c shows the simulated gate charge for the reference device 510 and for the novel power MOSFET device 509. The overall gate charge is reduced in the novel disclosed design thanks to the reduction of the Miller plateau duration, which is a one-to-one representative of the gate-to-drain capacitance reduction.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.