TECHNICAL FIELD

[0001] This application relates to a vertical channel-all-around metal-antiferroelectric- metal-insulator-semiconductor (MAMIS) field effect transistor and a method for manufacturing the same. This application also relates to a semiconductor device that includes a plurality of the vertical channel all-around MAMIS field effect transistors and a method for manufacturing the semiconductor device.

BACKGROUND

[0002] Field effect transistors (FETs) function by utilizing an electric field to regulate the electrical characteristics of the transistor. Vertical FETs typically comprise a vertical channel with active source and drain regions positioned both below and above the vertical channel. Such FETs may be used in the design of non-volatile memories (NVMs) as vertical FETS may be more effectively scaled down to smaller sizes and may be more easily stacked therefore allowing the NVMs to have higher transistor density and improved performance.

SUMMARY

[0003] In one aspect, the present disclosure describes vertical field effect transistor (FET) comprising a gate structure having a first end and a second end, an antiferroelectric layer surrounding the gate structure, a floating-gate layer surrounding the antiferroelectric layer, a dielectric layer disposed around the metal layer, and a channel layer disposed around the dielectric layer, wherein a plane direction of the antiferroelectric layer, the floating-gate layer, the dielectric layer, and the channel layer are all in a perpendicular direction to an extension direction of the gate structure. The vertical FET also includes a source structure that contacts the channel layer proximate the first end of the gate structure, a drain structure that contact the channel layer proximate the second end of the gate structure and an isolation layer disposed between the source and the drain structures.

[0004] In a further embodiment of this aspect, the present disclosure describes a semiconductor device comprising a plurality of the vertical field effect transistors wherein each of the gate structures of the vertical field effect transistors have the same extension direction.

[0005] In yet a further embodiment of this aspect, the present disclosure describes a semiconductor device comprising a plurality of the vertical field effect transistors wherein each of the gate structures of the vertical field effect transistors have the same extension direction. A first set of the vertical field effect transistors of the plurality of the vertical field effect transistors are spaced apart along a direction perpendicular to the extension direction of the gate structures of the vertical field effect transistors, and a second set of the vertical field effect transistors of the plurality of the vertical field effect transistors are spaced apart along a direction perpendicular to the extension direction of the gate structures of the vertical field effect transistors. Additionally, each of the gate structures of the first set of vertical field effect transistors are stacked to a corresponding gate structure of the second set of vertical field effect transistors.

[0006] In another aspect, the present disclosure describes a semiconductor device comprising a layered stack structure having a plurality of metal-insulator-metal (MIM) layers, and a plurality of isolation layers where the MIM layers and the isolation layers are stacked such that each isolation layer is stacked on an upper layer of each of the plurality of MIM layers. The semiconductor device also has a via extending from an upper surface of the layered stack structure to a lower surface of the layered stack structure and the via has a plurality of recesses formed at sidewalls of the via at each of the MIM layers. Further, the semiconductor device has a channel layer disposed within the recesses contacting the plurality of MIM layers; a dielectric layer disposed within the recesses contacting the channel layer; a floating-gate layer disposed within the recesses contacting the dielectric layer; an antiferroelectric layer disposed within the via contacting the plurality of isolation layers, the channel layers, the dielectric layers, and the floating-gate layers; and a gate structure formed within the via contacting the antiferroelectric layer.

[0007] In another aspect, the present disclosure describes a method for forming a vertical field effect transistor, the method comprising the steps of depositing a layered stack onto a substrate, the layered stack comprising a first metal layer, an insulator layer deposited on the first metal layer, a second metal layer deposited on the insulator layer and a protective layer deposited on the insulator layer; forming a hole from an upper surface of the layered stack to a lower surface of the layered stack; forming a recess in a sidewall of the hole at the first metal layer, the insulator layer, and the second metal layer; depositing a channel layer over all exposed surfaces in the recess of the layered stack; depositing a dielectric layer over the channel layer in the recess; filling the recess with a floating-gate layer; depositing an antiferroelectric layer over all exposed surfaces in the hole of the layered stack; and filling the hole with a third metal layer to form a gate structure of the vertical field effect transistor. [0008] In yet another aspect, the present disclosure describes a method for forming a semiconductor device having a plurality of vertical field effect transistors, wherein each gate structure of the vertical field effect transistors has the same extension direction, and wherein the vertical field effect transistors are spaced apart along a direction perpendicular to the extension direction of the gate structures of the vertical field effect transistors, the method comprising the steps of depositing a layered stack onto a substrate, the layered stack comprising a first metal layer, an insulator layer deposited on the first metal layer, a second metal layer deposited on the insulator layer and a protective layer deposited on the insulator layer; forming a plurality of holes from an upper surface of the layered stack to a lower surface of the layered stack. For each of the plurality of holes, the method then includes the steps of forming a recess in a sidewall of the hole at the first metal layer, the insulator layer, and the second metal layer; depositing a channel layer over all exposed surfaces in the recess of the layered stack; depositing a dielectric layer over the channel layer in the recess; filling the recess with a floating-gate layer; depositing an antiferroelectric layer over all exposed surfaces in the hole of the layered stack; and filling the hole with a third metal layer to form a gate structure of the vertical field effect transistor.

[0009] In still yet another aspect, the present disclosure describes a method for forming a semiconductor device comprising the steps of depositing a layered stack structure comprising a plurality of metal-insulator-metal (MIM) layers, and a plurality of isolation layers on a substrate where the MIM layers and the isolation layers are stacked such that each isolation layer is stacked on an upper layer of each of the plurality of MIM layers. The method then comprises the step of forming a via extending from an upper surface of the layered stack structure to a lower surface of the layered stack structure; etching a plurality of recesses at the sidewalls of the via at each of the MIM layers; forming a channel layer within the recesses contacting the plurality of MIM layers; forming a dielectric layer within the recesses contacting the channel layer; forming a floating-gate layer within the recesses contacting the dielectric layer; forming an antiferroelectric layer within the via contacting the plurality of isolation layers, the channel layers, the dielectric layers, and the floating-gate layers; and filing the via with a third metal layer to form a gate structure contacting the antiferroelectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments of the present disclosure are described below with reference to the following drawings:

Fig. 1A illustrates a perspective view of a vertical channel-all-around field effect transistor in accordance with an embodiment of the present disclosure; Fig. 1B illustrates a top view of the vertical channel-all-around field effect transistor in accordance with an embodiment of the present disclosure;

Fig. 2A illustrates a cut-off perspective view of the vertical channel-all-around field effect transistor in accordance with embodiments of the present disclosure;

Fig. 2B illustrates a partially cut-off side view of the vertical channel-all-around field effect transistor in accordance with embodiments of the present disclosure;

Fig. 3 illustrates a plot of measured drain current to gate-source voltage of a vertical channel- all-around field effect transistor for various area ratios;

Fig. 4 illustrates a plot of the simulated memory window of a vertical channel-all-around field effect transistor when the floating gate thickness is varied with respect to the thickness of the gate structure;

Fig. 5 illustrates plots showing the endurance of a fabricated antiferroelectric capacitor with AI/HZO/W structures when the cycling voltages are varied;

Fig. 6 illustrates plots showing the distribution of free energy relative to the polarization effect, and polarization relative to the electric field in an antiferroelectric capacitor and two different MAM layers;

Fig. 7 illustrates a flowchart of a process to form a vertical channel-all-around field effect transistor in accordance with an embodiment of the present disclosure;

Fig. 8 illustrates a flowchart of a process to form a semiconductor device having a plurality of the vertical channel-all-around field effect transistors in accordance with an embodiment of the present disclosure;

Fig. 9 illustrates a flowchart of a process to form a semiconductor device having a single memory string comprising a plurality of the vertical channel-all-around field effect transistors in accordance with an embodiment of the present disclosure;

Figs. 10A-10I illustrate the process to form vertical channel-all-around field effect transistors in accordance with an embodiment of the invention;

Fig. 11 illustrates a structure of a semiconductor device that has multiple memory strings that each comprise a plurality of the vertical CAA MAMIS FETs as memory cells; and

Fig. 12 illustrates an equivalent circuit schematic of the semiconductor device illustrated in Fig. 11.

DETAILED DESCRIPTION

[0011] The following detailed description is made with reference to the accompanying drawings, showing details and embodiments of the present disclosure for the purposes of illustration. Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments, even if not explicitly described in these other embodiments. Additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0012] In the context of various embodiments, the articles “a”, “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements.

[0013] In the context of various embodiments, the term “about” or “approximately” as applied to a numeric value encompasses the exact value and a reasonable variance as generally understood in the relevant technical field, e.g., within 10% of the specified value.

[0014] As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0015] As used herein, “comprising” means including, but not limited to, whatever follows the word “comprising”. Thus, use of the term “comprising” indicates that the listed elements are required or mandatory, but that other elements are optional and may or may not be present.

[0016] As used herein, “consisting of” means including, and limited to, whatever follows the phrase “consisting of”. Thus, use of the phrase “consisting of” indicates that the listed elements are required or mandatory, and that no other elements may be present.

[0017] In the context of various embodiments, the term “surround” means to enclose something completely to form a barrier around it. Thus, the use of the term “surround” indicates that something is on all sides of another thing.

[0018] In the context of various embodiments, the term “around” means to be in the proximity or location of something and does not necessarily mean that something has been completely encircled, but a large portion of the thing has been covered.

[0019] In the context of various embodiments, the directional terms mentioned herein, such as “above” and “below” or “upper” and “lower” refer to directions as described with reference to the drawings. Therefore, the directional terms are only used for illustration and are not meant to limit the present disclosure. [0020] In the context of various embodiments, it should be noted that when a material compound is described, such as HfZrC>2, the description refers to combinations of the listed elements. For example, Hf _x Zri. _x 02 encompasses various ratios of hafnium and zirconium within the compound where x can be equal to or less than 1 , among other possibilities.

[0021] It should be noted that although the terms first, second and third are used herein to describe various elements, these elements should not be limited by these terms as these terms are meant to only distinguish one element from another element. Thus, the first element described herein could be termed as a second element without departing from this disclosure.

[0022] As used herein, a “layer” refers to a material portion including a region having a particular thickness. The layer may extend over the entirety of the structure or may cover only part of the structure as defined in the description. For example, a layer may be located between two horizontal planes; may be located between, or at, a top surface and a bottom surface of the structure. The layer may also extend horizontally, vertically, and/or along the surface of the structure.

[0023] As used herein, a “stack” refers to a vertical arrangement or a structure that comprises multiple layers of different materials or similar materials of films that are deposited onto one another.

[0024] Additionally, for the sake of brevity, extensive explanations of conventional techniques of fabricating semiconductor devices and integrated circuits are not described in detail herein. The tasks and processes described herein may also be integrated into a more comprehensive procedure with extra steps of features that are not elaborated upon in this document. Specifically, certain processes of fabricating semiconductor devices are well known to one skilled in the art hence, such processes will be omitted entirely.

[0025] A material that exhibits antiferroelectric properties may be described as a crystal with two sublattices that have equal and opposite polarization. When no electric field is applied, the dipoles in these sublattices cancel each other out, resulting in a net polarization of zero. When an electric field is applied, a ferroelectric phase can be induced in the material.

[0026] Therefore, in order to utilize antiferroelectric materials in the gate stack of nonvolatile memories (NVMs), there has to be a built-in potential at the gate stack of the memory and this built-in potential may be induced by a work function difference between two metal layers within the gate stack. This built-in potential is responsible for the polarization switching or data storage mechanism in the antiferroelectric material (in the gate stack), enabling this material to be used in the manufacture of an antiferroelectric memory device. By harnessing this built-in potential at the gate stack, a memory device that can retain and store data without the need for a continuous power supply can be manufactured from antiferroelectric materials.

[0027] A perspective view of a vertical channel all-around (CAA) metal-antiferroelectric- metal-insulator-semiconductor (MAMIS) field effect transistor (FET) in accordance with an embodiment of the present disclosure is illustrated in Fig. 1 A wherein such a vertical FET may be used in the fabrication of a semiconductor device structure containing vertical NAND memory devices. As illustrated, vertical CAA MAMIS FET 100 comprises control gate 102 that is coupled to gate structure 103. In embodiments of the disclosure, control gate 102 and gate structure 103 may comprise, but are not limited to, metals such as Tungsten (W), Ruthenium (Ru), Platinum (Pt), Titanium Nitride (TiN), Molybdenum (Mo), Tantalum (Ta) or any metals that may be deposited using an Atomic Layer Deposition (ALD) process.

[0028] Vertical CAA MAMIS FET 100 also has a layered gate-stack 108 that surrounds gate structure 103. As illustrated, it can be seen that a plane direction of layered gate-stack 108 extends along a direction that is perpendicular to the extension direction of gate structure 103. In an embodiment of the disclosure, layered gate-stack 108 comprises an antiferroelectric layer that surrounds gate structure 103, a floating-gate layer that surrounds the antiferroelectric layer, a dielectric layer that surrounds the floating-gate layer, and a channel layer that is disposed around the dielectric layer.

[0029] Vertical CAA MAMIS FET 100 are also provided with drain/source electrodes or structures 104 and 106 that contact a channel layer of within layered gate-stack 108 at the respective ends of gate structure 103. In embodiments of the disclosure, source/drain electrodes or structures 104 and 106 may comprise, but are not limited to, metals such as tungsten (W), titanium (Ti), nickel (Ni), and cobalt (Co). Fig. 1 B illustrates a top view of the vertical CAA MAMIS FET that was illustrated in Fig. 1A. This top view clearly shows all the layers in layered gate-stack 108.

[0030] A cut-off perspective view of vertical CAA MAMIS FET 100 as illustrated in Fig. 1A is illustrated in Fig. 2A and a cut-off side view of the vertical CAA MAMIS FET is illustrated in Fig. 2B. As can be seen from Fig. 2A and 2B, layered gate-stack 108 comprises antiferroelectric layer 111 that surrounds gate structure 103, floating-gate layer 112 that surrounds antiferroelectric layer 111 , dielectric layer 113 that surrounds floating-gate layer 112, and channel layer 114 that is disposed around dielectric layer 113. In short, layered gatestack 108 comprises a metal-antiferroelectric-metal-insulator-semiconductor (MAM IS) layered stack where the innermost layer of the vertical CAA MAM IS FET comprises the metal layer. Drain/source electrodes 104 and 106 that contact channel layer 114 are then disposed around the respective ends of gate structure 103.

[0031] In embodiments of the disclosure, a cross section of gate structure 103 may comprise a circle, an ellipse, or any irregular shape without departing from this disclosure. Further, antiferroelectric layer 111 may comprise, but is not limited to, a hafnium zirconium oxide (HfxZr1-xO2) compound, where x may be less than 0.3, and dielectric layer 113 may comprise, but is not limited to Hafnium dioxide (HfC>2), Aluminum oxide (AI2O3) or a high-k material. Still further, channel layer 114 may comprise, but is not limited to, Indium oxide (ln2Os), Zinc oxide (ZnO), Indium Tin oxide (ITO), a Low-Temperature Polycrystalline Silicon (LTPS) or any other semiconductor material that may be deposited using the ALD process to ensure adherence to the sidewall of a via/hole and floating gate layer 112 may comprise, but is not limited to, Tungsten (W), Ruthenium (Ru), Platinum (Pt), Titanium Nitride (TiN) or any other semiconductor material that may be deposited using the ALD process.

[0032] It should be noted that the material used for gate structure 103 is different from the material used for floating-gate layer 112. This is to ensure that a work function difference exists between these two metal layers in layered gate-stack 108. In embodiments of the disclosure, a method for work function tuning to ensure a work function difference exists between gate structure 103 and floating-gate layer 112 comprises the step of carefully adjusting the deposition process of the metal when these layers are formed. In embodiments of the disclosure, this may be done by adding some dopant to one of the layers during the deposition process or by ensuring that the metals of both layers are completely different. For example, when gate structure 103 is formed using Platinum (Pt) (which has a work function of about 5.5 eV), floating-gate layer 112 may then be formed using Titanium Nitride (TiN) (which has a work function of about 4.5 eV). It should be noted that the work function of the metal formed is dependent on the deposition process and the subsequent fabrication processes. Additionally, the work difference between these two metal layers is also affected by the properties of antiferroelectric layer 111 and its thickness. For example, if antiferroelectric layer 111 comprises Hfo.2Zro.8O2 with a thickness of 10 nm, the work function difference between the two metal layers would then be between 1 to 1.5 eV. It should be noted that this work difference decreases when the thickness of antiferroelectric layer 111 decreases. [0033] Layered gate-stack 108 allows for the capacitance ratio formed by the metal- antiferroelectric-metal capacitor (gate structure 103 - antiferroelectric layer 111 - floating gate layer 112) and the metal-insulator-semiconductor capacitor (floating gate layer 112 - dielectric layer 113 - channel layer 114) to be tuned as required, as these capacitance ratios will influence the voltage distribution when the vertical CAA MAMIS FET is used as a memory cell in non-volatile memory devices. In comparison to conventional designs that lack a floating gate layer I floating metal layer or an insulator layer, the structure of vertical CAA MAMIS FET 100 offers several advantages, including the potential for an increased memory window (MW), a higher on/off ratio, and improved endurance. However, the experimental results presented in Fig. 3 highlight the need for careful device design in order to achieve optimal performance with a larger MW. It should be noted that the devices used to obtain the results shown in Fig. 3 comprise planar metal-antiferroelectric-metal-insulator-semiconductor (MAMIS) FETs with a similar structure as vertical CAA MAMIS FET 100 whereby the area ratios of these devices have been varied.

[0034] The area ratio (AR) of such a FET is defined as the area of an antiferroelectric (AFe) capacitor (which is formed by the gate structure, floating gate and the AFe layer in between) divided by the area of the transistor part (which for a typical FET is formed by the floating gate, dielectric layer, channel layer and the source/drain). Therefore, by tuning the size of the gate structure, devices with different ARs can be realized.

[0035] In embodiments of the disclosure, the electrical characteristics of the MAMIS FETs were measured using a semiconductor parameter analyzer (such as a 4200a-SCS, KEITHLEY). The curves shown in Fig. 3 represent the transfer characteristics of the devices mentioned above where each plot corresponds to a device with a specific AR. In addition to the typical drain current (ID) to gate-to-source voltage (VGS) characterizations, a dual-sweep VGS was applied in order to plot the hysteresis loops. The application of a dual-sweep voltage implies that the gate-to-source voltage (VGS) was swept with one cycle of an alternating voltage. For example, the gate-to-source voltage may be swept from -5 V to 5 V and then from 5 V to -5 V. From the plots, it can be seen that non-volatility is achieved when the gate structure comprises Tungsten (W) and when the floating gate comprises Aluminum (Al) with various area ratios. Additionally, these plots show that the memory window (MW) increases when the AR decreases. A memory window (MW) is defined as a separation of the high-conductance state and the low-conductance state threshold voltages (black dots 302 as labeled in the figure), and the MW can be obtained from the dual-sweep ID-VGS curves by setting a threshold drain current (e.g., 10' ⁴ pA/pm in Fig. 3). Basically, it can be seen that the hysteresis loop becomes more and more open, which indicates that the MW is increasing.

[0036] In planar devices, this often involves allocating a smaller area to the metal- antiferroelectric-metal capacitor and a larger area to the metal-insulator-semiconductor capacitor, necessitating a substantial surface area for the floating gate. It should be noted that the experimental measurements illustrated in Fig. 3 were performed on a planar CAA MAM IS FET for brevity and that these concepts may be applied to a vertical CAA MAMIS FET without departing from the embodiments in this disclosure.

[0037] Hence, the use of a vertical CAA MAMIS FET effectively addresses the issue of inefficient use of space while facilitating high-density integration of CAA MAMIS FETs into a memory device. This approach capitalizes on the inherent radius relationship between the inner and outer layers within the vertical CAA MAMIS FET, thereby enabling a sufficient voltage to drop across the antiferroelectric layer. This condition is essential for achieving a relatively saturated switching of the antiferroelectric material which leads to a superior memory performance characterized by a substantial memory window (MW) and on/off ratio. Fig. 4 depicts the simulated MW of the vertical CAA MAMIS FET, confirming its viability.

[0038] Two pivotal parameters that affect the capacitance ratios of the vertical CAA MAMIS FET are the radius of the gate structure and the thickness of the floating gate, and these parameters are chosen as the axes in the plot shown in Fig. 4. The grey-coded regions in the graph correspond to the MW of the respective device and the results clearly illustrate a tradeoff between MW and device area when the size of the gate structure is fixed. In other words, this plot shows that a gate structure with a smaller radius will result in a device with a larger MW. This emphasizes the need for deliberate design considerations prior to fabrication to strike a balance between achieving optimal performance and managing area-related costs.

[0039] Moreover, the utilization of antiferroelectric materials in place of their ferroelectric counterpart is driven by the objective of enhancing memory endurance. The relatively limited reliability of emerging non-volatile memories (NVMs) not only presents a significant hurdle to their practical application but also stands as a primary challenge in the context of nextgeneration computing systems that prioritize memory-centric architecture.

[0040] This improvement in endurance is attributed to the lower local depolarization field observed during the switching transient in antiferroelectric materials, resulting in reduced charge injection within the antiferroelectric layer. This, in turn, leads to a decrease in the occurrence of polarization fatigue and dielectric breakdown. The experimental data from fabricated antiferroelectric capacitor devices demonstrates an outstanding endurance, exceeding 1O ¹⁰ cycles with a bipolar voltage of 2 V, as illustrated in Fig. 5. The device used to generate the plots in Fig. 5 comprises a Hafnium Zirconium Oxide (HZO) capacitor 502 having a MAM layered structure comprising of AI/HZO/W. These results illustrate the outstanding endurance of non-volatile AFe capacitor. By implementing an optimized fabrication process and appropriate surface treatments, it is conceivable that the endurance of AFe devices could be further elevated.

[0041] Nevertheless, despite these advantages, an antiferroelectric-based device may not be a direct replacement for their ferroelectric counterparts in the fabrication of memory devices due to its inherent absence of remnant polarization at zero bias. To transform the proposed antiferroelectric memory into a non-volatile entity, a built-in potential has to be created within the antiferroelectric layer. To do so, a work function contrast is established in layered gatestack 108 by the deposition of dissimilar materials for each metal layer within the gate stack (i.e., different materials are used for the floating-gate layer and the gate structure). Fig. 6 illustrates the non-zero remnant polarization of the antiferroelectric layer at zero bias for an antiferroelectric capacitor comprising a metal-antiferroelectric-metal (MAM) layer made up of AI/HZO/W 604 and Pt/HZO/W 606. This polarization effect was achieved due to the inducement of the built-in potential. Additionally, Fig. 6 also shows the free energy in relation to the polarization of the antiferroelectric layer, whereby the P-V hysteresis shift of the antiferroelectric capacitor has been achieved through the engineering of the work function, i.e., by forming a metal-antiferroelectric-metal (MAM) layer comprising AI/HZO/W 604 and Pt/HZO/W 606 . It can be seen that the free energy of MAMs 604 and 606 have two valleys allowing for the existence of two possible states. As a baseline, the free energy and the polarization of an antiferroelectric layer 602 is plotted in Fig. 6 as well.

[0042] In an embodiment of the invention, an individual vertical CAA MAMIS FET may be fabricated as follows. A bottom electrode (source or drain) is first deposited by a process, such as sputtering, with a metal material having a particular work function to form an ohmic contact with a semiconductor region such as a substrate. In embodiments of the disclosure, the substrate may comprise, but is not limited to, Silicon, Silicon Germanium, Silicon Carbide, Silicon dioxide, Aluminum dioxide, undoped Silicon or any other suitable materials. In an embodiment of this disclosure, the substrate may comprise a low work function value when the channel layer comprises a n-type semiconductor. After patterning the bottom electrode by an etching process, a dielectric layer comprising Silicon dioxide (SiC>2) and a top electrode (source/drain) are sequentially deposited by a deposition process such as sputtering or chemical vapor deposition (CVD). Hence, a triple layered structure, i.e., a metal/insulator/metal (MIM) structure is thus formed. A protective layer, comprising Silicon dioxide or Aluminum oxide, is then deposited on the top electrode. In embodiments of the disclosure, the thickness of the bottom and top electrodes may be between 30 nm and 40 nm, and the thickness of the dielectric layer may be between 30 nm and 40 nm. At the next stage, this triple layered structure with the protective layer is etched to form a hole through the triple layer structure.

[0043] The bottom electrode, the insulator layer, and the upper electrode are then etched from the sidewall of the hole forming a recessed region in the sidewall of the hole. Once the etched hole with the recess has been formed, a channel film comprising a semiconductor material such as Indium Gallium Zinc Oxide (IGZO) or Low-Temperature Polycrystalline Silicon (LTPS) having a thickness around 10 nm or less, a dielectric layer with high-k material such as HfO2 having a thickness around 5 nm, and a floating gate layer with metal such as W or TiN are each sequentially deposited in turn into the hole. In embodiments of the disclosure, as isotropic deposition is preferred, atomic layer deposition (ALD) shall be used. Similarly, the antiferroelectric layer with Hf _x Zri. _x 02 (HZO) is then deposited into the hole using ALD with a proper Hf to Zr ratio for antiferroelectricity. Typically, the x shall be less than 0.3. Finally, the hole is filled with a metal material to form the gate structure and the resulting device is patterned to complete the vertical CAA MAMIS FET structure. As a last step, the vertical CAA MAMIS FET undergoes a thermal treatment process to activate the channel layer and to form the antiferroelectric phase within the antiferroelectric layer.

[0044] A process for fabricating an individual vertical CAA MAMIS FET in accordance with an embodiment of this disclosure is illustrated in Fig. 7. Process 700 may be performed using standard semiconductor fabrication or manufacturing steps. Process 700 begins at step 702 where a layered stack is first deposited onto a substrate. The bottom layer of the layered stack comprises a first metal layer, an insulator layer deposited on the first metal layer, a second metal layer deposited on the insulator layer and a protective layer deposited on the second metal layer.

[0045] At step 704, process 700 etches a hole or a via through the layered stack to the substrate. Process 700 then proceeds to etch the first and second metal layers and the insulator layer from the sidewall of the hole thereby forming a recess in the sidewall of the hole. This takes place at step 706. At step 708, a channel layer is then deposited into the hole, covering all exposed surfaces in the hole, including the recessed area of the hole’s sidewall. Process 700 then proceeds to deposit a dielectric layer over the channel layer at step 710. At step 712, the recess is then filled with a floating gate layer. Process 700 then fills the hole with an antiferroelectric layer thereby covering all surfaces in the hole including the hole’s sidewalls. This takes place at step 714. Finally, at step 716, process 700 fills the hole with a third metal layer that is then later on patterned to form the gate structure of the vertical CAA MAMIS FET. Process 700 then ends. In embodiments of the disclosure, drain/source structures may be electrically connected to the first metal layer and the second metal layer.

[0046] A process for fabricating a semiconductor device having a plurality of vertical CAA MAMIS FETs in accordance with an embodiment of this disclosure is illustrated in Fig. 8. Similarly, process 800 may be performed using standard semiconductor fabrication or manufacturing steps. Process 800 begins at step 802 where a layered stack is first deposited onto a substrate. The bottom layer of the layered stack comprises a first metal layer, an insulator layer deposited on the first metal layer, a second metal layer deposited on the insulator layer and a protective layer deposited on the second metal layer.

[0047] At step 804, process 800 etches a plurality of holes or vias through the layered stack to the substrate. Process 800 then proceeds to etch the first and second metal layers and the insulator layer from the sidewalls of the holes such that these three layers are narrower than the protective layer thereby forming a recess in each of the sidewalls of the holes. This takes place at step 806. At step 808, a channel layer is then deposited into the holes, covering all exposed surfaces in the holes, including the recessed area of each hole’s sidewall. Process 800 then proceeds to deposit a dielectric layer over the channel layer at each of the holes at step 810. At step 812, the recess in each of the holes is then filled with a floating gate layer. Process 800 then fills the holes with an antiferroelectric layer thereby covering all surfaces in the holes including each hole’s sidewalls. This takes place at step 814. Finally, at step 816, process 800 fills the holes with a third metal layer that is then later on patterned to form the various gate structures of the plurality of vertical CAA MAMIS FETs. Process 800 then ends.

[0048] A process for fabricating a semiconductor device having a single memory string comprising a plurality of the vertical CAA MAMIS FETs in accordance with an embodiment of this disclosure is illustrated in Fig. 9. In embodiments of the disclosure, this semiconductor device may be a non-volatile memory (NVM) device. Process 900 may be performed using standard semiconductor fabrication or manufacturing steps. Process 900 begins at step 902 where a layered stack structure comprising a plurality of metal-insulator-metal (MIM) layers, and a plurality of isolation layers are deposited onto a substrate. The MIM layers and the isolation layers are stacked such that each isolation layer is stacked on an upper surface of each of the MIM layers.

[0049] At step 904, process 900 forms a via extending from an upper surface of the layered stack structure to a lower surface of the layered stack structure. Process 900 then proceeds to etch a plurality of recesses at the sidewalls of the via at each of the MIM layers at step 906. At step 908, process 900 then deposits a channel layer material within the recesses, forming a channel layer that contacts the plurality of MIM layers. Process 900, at step 910, then deposits a dielectric layer material within the recesses, forming a dielectric layer that contacts the channel layer. At step 912, process 900 then fills each recess with a floating-gate layer material, forming a floating-gate layer within the recesses that contact the dielectric layer. Process 900 then deposits an antiferroelectric layer over all surfaces in the via, forming an antiferroelectric layer within the via that contacts the plurality of isolation layers, the channel layers, the dielectric layers, and the floating-gate layers. This takes place at step 914. Finally, at step 916, process 900 then fills the via with a third metal layer to form a gate structure that contacts the antiferroelectric layer. Process 900 then ends.

[0050] In accordance with embodiments of the disclosure, a semiconductor device such as a high-density integrated memory array having the above-mentioned vertical CAA MAMIS FET as the memory cells may be fabricated as shown in Figs. 10A-I.

[0051] Firstly, as illustrated in Fig. 10A, multiple layered stacks (that each comprise metal/insulator/metal/protective layers) are deposited onto substrate 1002 using well-known processes such as sputtering, CVD, or ALD. In embodiments of the disclosure, insulator layer 1004 may comprise a type of nitride and protective layer 1006 may comprise a type of oxide.

[0052] Next, as illustrated in Fig. 10B, a memory-string hole 1008 is formed through all the layers using a dry-etching process for a high aspect ratio. After the metal layers and the insulator layer disposed in-between the metal layers are etched using an isotropic etching process to form recesses 1010, the channel 114, dielectric 113, and floating gate 112 layers are sequentially deposited using the ALD process for conformal covering. These steps are sequentially illustrated in Figs. 10C to 10F. [0053] As illustrated in Fig. 10G, another dry etching step is then carried out to etch away the floating gate layer 112 in hole 1008 such that each of the vertical CAA MAMIS FETs within the memory string are isolated from each other. After that, the antiferroelectric layer 111 is deposited over the exposed surfaces of hole 1008, including the sidewalls of the hole, leaving a cavity 1012 behind. This is illustrated in Fig. 10H. The last metal layer (which forms gate structure 103) is then deposited into cavity 1012 until cavity 1012 is filled with the metal as shown in Fig. 101. The resulting device is then treated with thermal processes to activate the channel layer and the phase formation of the antiferroelectric layer. The pattern of the electrodes will then be made during the final process to form the array structure with extruded source/drain and control gate electrodes connected to the peripherals. One skilled in the art will recognize that although Figs. 10A-10I only illustrates the process to fabricate a single memory string with a plurality of vertical CAA MAMIS FETs, the processes shown in Figs. 10A-10I may be used to fabricate a plurality of memory strings and their corresponding vertical CAA MAMIS FETs without departing from this disclosure.

[0054] The structure of a three-dimensional (3D) integrated memory that utilizes the plurality of vertical CAA MAMIS FETs is illustrated in Fig. 11 and its equivalent circuit schematic is illustrated in Fig. 12. As illustrated in Figs. 11 and 12, it can be seen that unlike conventional 3D NAND flash structures that utilize FETs (or memory cells) with a single shared channel and separated gates, semiconductor device 1100 utilizes shared gates (where the gates of the FETs are all electrically connected together) with the source/drain structures being separated for each of the FETs (or memory cells). Specifically, in each memory string, the gate structure of each vertical CAA MAMIS FET is stacked to a corresponding gate structure of another vertical CAA MAMIS FET.

[0055] Additionally, in semiconductor device 1100, it can be seen that each of the gate structures of the vertical CAA MAMIS FETs have the same extension direction and each of the vertical CAA MAMIS FETs are spaced apart along a direction perpendicular to the extension direction of the gate structures of the vertical field effect transistors. In embodiments of the disclosure, the spacing between the vertical FETs may be between 100 nm to 300 nm (center to center distance).

[0056] In embodiments of the disclosure, a single memory string of semiconductor device 1100 may comprise a layered stack structure comprising a plurality of metal-insulator-metal (MIM) layers, and a plurality of isolation layers, the MIM layers and the isolation layers being stacked such that each isolation layer is stacked on an upper layer of each of the plurality of MIM layers. The semiconductor device has a via extending from an upper surface of the layered stack structure to a lower surface of the layered stack structure and the via has a plurality of recesses formed at sidewalls of the via at each of the MIM layers. The semiconductor device also has a channel layer disposed within the recesses contacting the plurality of MIM layers; a dielectric layer disposed within the recesses contacting the channel layer; a floating-gate layer disposed within the recesses contacting the dielectric layer; an antiferroelectric layer disposed within the via contacting the plurality of isolation layers, the channel layers, the dielectric layers, and the floating-gate layers; and a gate structure formed within the via contacting the antiferroelectric layer. In embodiments of the disclosure, this semiconductor device may be a non-volatile memory (NVM) device.

[0057] In embodiments of the disclosure, semiconductor device 1100 comprising multiple memory strings may have a layered stack structure comprising a plurality of metal-insulator- metal (MIM) layers, and a plurality of isolation layers, the MIM layers and the isolation layers being stacked such that each isolation layer is stacked on an upper layer of each of the plurality of MIM layers. The semiconductor device also has a plurality of vias extending from an upper surface of the layered stack structure to a lower surface of the layered stack structure wherein each of the vias has a plurality of recesses formed at sidewalls of each of the vias at each of the MIM layers. The semiconductor device also has a channel layer disposed within each of the recesses contacting the plurality of MIM layers; a dielectric layer disposed within each of the recesses contacting the channel layer; a floating-gate layer disposed within each of the recesses contacting the dielectric layer; an antiferroelectric layer disposed within each of the vias contacting the plurality of isolation layers, the channel layers, the dielectric layers, and the floating-gate layers; and a gate structure formed within each of the vias such that the gate structure contacts the antiferroelectric layer. In embodiments of the disclosure, this semiconductor device may be a non-volatile memory (NVM) device.

[0058] Such a configuration allows the proposed design to have random-access capability, which makes it promising for the future computing applications, such as in-memory computing and neuromorphic computing.

[0059] Numerous other changes, substitutions, variations, and modifications may be ascertained by the skilled in the art and it is intended that the present application encompass all such changes, substitutions, variations and modifications as falling within the scope of the appended claims.