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Title:
METHOD FOR FORMING BURIED BIT LINE, MEMORY AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/082422
Kind Code:
A1
Abstract:
A method for forming a buried bit line, a memory and a manufacturing method therefor, and an electronic device. The memory comprises a plurality of transistors, and further comprises: a first dielectric layer (41), a second dielectric layer (42), and a third dielectric layer (43) which are sequentially arranged on a substrate (10), wherein the first dielectric layer (41) and the third dielectric layer (43) are oxide layers, and the second dielectric layer (42) is a nitride layer; a plurality of first trenches (51) extending in a column direction and arranged in a row direction at intervals and a plurality of second trenches (52) extending in the row direction and arranged in the column direction at intervals, the first trenches (51) and the second trenches (52) being formed in the substrate (10), and the first trenches (51) extending into the second dielectric layer (42) to a set depth; a plurality of semiconductor pillars (20) having one-to-one correspondence to the transistors and arranged in the row and column directions at intervals, each column of semiconductor pillars (20) being arranged in one first trench (51); and a plurality of bit lines (30) arranged in the first trenches (51) and extending in the column direction, the semiconductor pillars (20) being located on the bit lines (30) and connected to the bit lines (30).

Inventors:
LIU ZHAO (CN)
Application Number:
PCT/CN2022/140176
Publication Date:
April 25, 2024
Filing Date:
December 19, 2022
Export Citation:
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Assignee:
BEIJING SUPERSTRING ACADEMY OF MEMORY TECH (CN)
CXMT CORP (CN)
International Classes:
H01L29/78; H01L29/66; H10B12/00
Foreign References:
US20130234242A12013-09-12
CN114709168A2022-07-05
CN103681510A2014-03-26
CN114068549A2022-02-18
CN103545313A2014-01-29
Attorney, Agent or Firm:
AFD CHINA INTELLECTUAL PROPERTY LAW OFFICE (CN)
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