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WO/2024/082729A1 |
In an approach to improve write transducers a write transducer for recording data on a magnetic media is disclosed. The write transducer comprises a first pole piece. The write transducer further comprises a second pole piece. The first ...
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WO/2024/086092A1 |
A stacked die device includes a first master dynamic random access memory (DRAM) die having a first command interface to receive first commands and a first data interface to transfer first data. A second master DRAM die is stacked with t...
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WO/2024/086753A2 |
A rack mountable enclosure may be suitable for mounting and enclosing electrical equipment, including electronic servers. The enclosure may include a locking bezel to cover and protect user accessible features from tampering. The enclosu...
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WO/2024/082455A1 |
Embodiments of the present disclosure provide a memory device, comprising: a cyclic redundancy check (CRC) circuit (200) configured to indicate whether a CRC error has been detected from data transmission of a host device and the memory ...
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WO/2024/082343A1 |
A memory refresh parameter determination method, comprising: for each memory unit in a semiconductor to be tested, determining the time ratio of a data retention duration of the memory unit to a reference data retention duration of a ref...
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WO/2024/082527A1 |
Provided in the embodiments of the present disclosure are a delay phase-locked loop and a memory. When starting to operate, the delay phase-locked loop determines a phase difference between a reference clock signal and a feedback clock s...
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WO/2024/084430A1 |
An audio reproduction desk comprises a table with a tabletop (110) which lies at a height and has a left-hand loudspeaker panel (140L) and a right-hand loudspeaker panel (140L) which extend upward substantially mirrored relative to the c...
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WO/2024/082562A1 |
The embodiments of the present disclosure provide a sense amplifier, a control method therefor, and a memory, the control method comprising: in a sense amplification stage of a sense amplifier, turning on X pull-up units and/or turning o...
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WO/2024/085619A1 |
The present invention pertains to a hologram recording medium, and an optical element including said hologram recording medium, wherein before light irradiation, the adhesion between a photopolymer layer and an adhesive protective layer ...
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WO/2024/085886A1 |
The invention provides a system and a computer-implemented method starting a video generating application, and then opening a camera and providing camera tutorials. The camera tutorials comprise instructions for camera positioning, camer...
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WO/2024/082102A1 |
An array substrate, a display apparatus, and a driving method. The array substrate comprises a gate driving circuit (110), wherein the gate driving circuit (110) comprises a plurality of cascaded shift register units. The driving method ...
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WO/2024/083036A1 |
Embodiments of present invention provide a magnetic tunnel junction (MTJ) structure. The MTJ structure includes a MTJ stack, the MTJ stack including a tunnel barrier layer on a reference layer and a free layer on the tunnel barrier layer...
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WO/2024/086104A1 |
As information is written to a memory device stack, partial parity information is calculated by the non-parity devices in the stack from the information being written to that device and parity information received from the next lower dev...
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WO/2024/082812A1 |
The present application relates to the field of semiconductor device testing, and discloses an FPGA storage unit failure analysis method and apparatus, an electronic device, and a storage medium. The FPGA storage unit failure analysis me...
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WO/2024/086409A1 |
An integrated circuit (IC) including a first transceiver interface circuit extending longitudinally in a first direction substantially perpendicular to a second direction parallel to edge of the IC, wherein the first transceiver interfac...
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WO/2024/082566A1 |
A ZQ calibration method and a ZQ calibration circuit. When being applied to a wafer-level semiconductor chip, the ZQ calibration method comprises: after a target chip is powered on, recognizing whether the target chip has been set to be ...
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WO/2024/084094A2 |
The invention relates to an assembly of a pulse-width-controlled vector-matrix multiplication unit and to a method for controlling said assembly, in which assembly an input block is connected to the word lines of a matrix composed of non...
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WO/2024/082466A1 |
Disclosed in embodiments of the present disclosure are a memory system and an operation method therefor, a memory controller, and a memory. The memory system comprises a memory; the memory comprises a memory cell array and a peripheral c...
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WO/2024/080574A1 |
An impedance calibration device according to an embodiment of the present disclosure comprises: a target driver module including a pull-up resistor circuit and a pull-down resistor circuit; a resistance measurement module for measuring e...
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WO/2024/078102A1 |
The present application relates to a memory chip, a memory device and an electronic device. The memory chip (20) comprises a plurality of memory units (210), each memory unit (210) comprising a substrate (21) and a plurality of memory su...
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WO/2024/079575A1 |
Provided is a semiconductor device having a novel configuration. This semiconductor device has: a first element layer having a bit line drive circuit; a second element layer having a first switch circuit, a first memory cell, and first w...
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WO/2024/077917A1 |
Disclosed in the embodiments of the present disclosure are an anti-fuse unit and an anti-fuse array. The anti-fuse unit comprises: an active region and at least one anti-fuse gate electrode. The active region extends in a first direction...
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WO/2024/077866A1 |
The present application is applied to the technical field of storage. Disclosed are a memory mapping method, system and device, and a storage medium. The method comprises: receiving a message, which is sent by a host, and analyzing the m...
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WO/2024/077659A1 |
Disclosed in embodiments of the present disclosure are a row address decoding circuit and a memory. The row address decoding circuit comprises N memory address control circuits, and N is greater than or equal to 1. Each memory address co...
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WO/2024/077800A1 |
Provided in the present disclosure are a clock generation circuit and a memory. The clock generation circuit comprises: a sampling module, which samples continuous chip selection signals on the basis of a sampling clock to acquire odd da...
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WO/2024/077695A1 |
A reliability test apparatus and a reliability test method, relating to the technical field of integrated circuits. The reliability test apparatus comprises: a test chip (210) and a test board (220), wherein at least part of chip metal p...
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WO/2024/080224A1 |
This magnetic tape drive is used in a magnetic tape cartridge which is equipped with a magnetic tape and a storage medium. The storage medium stores geometric characteristic information. The magnetic tape records geometric characteristic...
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WO/2024/078231A1 |
Disclosed are a data protection circuit, method and apparatus, and an electronic device and a storage medium. The data protection circuit comprises a front-end power supply port, a power-failure detection module and a communication modul...
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WO/2024/078853A1 |
A digital display device (Disp3a, Disp3b) comprising: - a digital screen (Ecr); - a first receiver (Rec1) able to receive a first piece of content via a first communication channel; - a second receiver (Rec2) able to receive a message vi...
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WO/2024/077684A1 |
A control circuit, comprising a random module (200) and an output module (100), wherein a first input end of the random module (200) receives a refresh count signal (CBR), a second input end thereof receives random data (rdmV), and a con...
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WO/2024/079816A1 |
A memory device in which, in a plan view, a plurality of pages are aligned in a column direction on a substrate and are formed by a plurality of memory cells aligned in a row direction, the memory device being characterized in that the m...
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WO/2024/077516A1 |
An electric power head includes: a body including a mounting flange defining a mounting plane; a battery compartment disposed in the body and configured to receive one or more electric power packs; an electric motor disposed in the body ...
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WO/2024/080223A1 |
According to the present invention, a first servo pattern has a first position and a second position at which the first servo pattern crosses with a virtual line. A second servo pattern has a third position at which the second servo patt...
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WO/2024/075416A1 |
A magnetic tape according to one embodiment of the present technology comprises a base material and a magnetic layer that is provided on one main surface of the base material; the base material is formed of a polyethylene naphthalate (PE...
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WO/2024/076850A1 |
A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors...
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WO/2024/075660A1 |
Provided is a magnetic recording medium with which a decrease in electromagnetic conversion characteristics can be suppressed.　This magnetic recording medium is a tape-like magnetic recording medium, and comprises a substrate and a mag...
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WO/2024/073907A1 |
Provided in the embodiments of the present disclosure are an ECS circuit, a method and a memory. The ECS circuit comprises an ECS control module, a command generation module, an address counting module and an error tracking and recording...
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WO/2024/075978A1 |
The present disclosure provides a sound source edit function provision method and a device supporting same, the method comprising operations of: receiving an original sound source including multiple sound source elements; selecting a pre...
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WO/2024/073904A1 |
Provided in the embodiments of the present disclosure are a counting control circuit, a counting control method, and a semiconductor memory. The counting control circuit comprises a logic control module and a counting statistical module,...
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WO/2024/073903A1 |
Provided in the embodiments of the present disclosure are a control circuit, a control method and a semiconductor memory. The control circuit comprises a timing control module and a command control module, and an output end of the timing...
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WO/2024/074936A1 |
Provided is a novel semiconductor device. This semiconductor device has a flip-flop group that includes n flip-flops, and a plurality of storage units. The flip-flop group has a function for saving n bits of data. One of the plurality of...
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WO/2024/073908A1 |
Embodiments of the present disclosure provide a delay control circuit and method, and a memory. The delay control circuit comprises a delay module. The delay module is configured to receive an initial command signal, and perform non-cloc...
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WO/2024/074968A1 |
Provided is a novel semiconductor device. The present invention comprises a flip-flop circuit and a memory circuit. The memory circuit comprises a first transistor, a second transistor, a first capacitance element, and a second capacitan...
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WO/2024/073909A1 |
Embodiments of the present disclosure provide a delay control circuit, a method, and a semiconductor memory. The delay control circuit comprises a decoding module and a delay module. The decoding module is configured to receive a mode re...
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WO/2024/073910A1 |
Embodiments of the present disclosure provide a delay control circuit and method, and a semiconductor memory. The delay control circuit comprises a clock module and a delay module; the clock module is configured to receive a temperature ...
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WO/2024/077021A1 |
An aromatic or aromatic-like group(s) containing lubricant configured to be adsorbed by a magnetic recording media is formed from ( Ar)m(R1oRfR2p)q where Ar is an aromatic group, polyaromatic hydrocarbon (PAH), annulene, cycloalkane or h...
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WO/2024/074901A1 |
Photonic content-addressable memories (CAMs) and applications thereof are provided. The CAM includes a photonic cross-bar array comprising a plurality of row and column waveguides, and a plurality of photonic filter devices. Each filter ...
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WO/2024/031798A9 |
Disclosed in the present invention are a high-bandwidth DDR dual-in-line memory module, and a memory system and an operation method therefor. The high-bandwidth DDR dual-in-line memory module comprises a first sub-channel, a second sub-c...
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WO/2024/076426A1 |
The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may engage a counting mode in which activat...
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WO/2024/072617A1 |
A system and method for redaction based on group association is disclosed. The method includes carrying out an analysis that includes coming to a determination that, notwithstanding at least some features of a plurality of group-associat...
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