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WO/2024/019825A1 |
An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a firs...
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WO/2024/020497A1 |
System, process and device configurations are provided for interface customized generation of gaming music. A method can include generating a musical accompaniment for electronic gaming by way of an interface. An interface is provided fo...
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WO/2024/016864A1 |
A processor, an information acquisition method, a single board and a network device, which relate to the technical field of computers. The processor comprises a control module (101), a first register (102) and a cache (103), and the proc...
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WO/2024/016855A1 |
Provided are a method and apparatus for determining a memory fault repair mode, and a storage medium. The method comprises: acquiring information of a plurality of row faults, wherein the information of the row faults comprises the seque...
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WO/2024/018556A1 |
A memory device in which, on a substrate in a plan view, a page is configured from a plurality of memory cells arranged in a row direction, and a plurality of the pages are arranged in a column direction, the memory device being characte...
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WO/2024/016939A1 |
A chip self-checking method and a chip. The chip comprises a self-checking module and a storage module. The chip self-checking method comprises: a self-checking module receives externally inputted address configuration parameter informat...
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WO/2024/016732A1 |
Provided in the present invention is a method for preparing a top electrode of a magnetic memory, the method comprising: providing a bottom structure, wherein the bottom structure has a patterned magnetic tunnel junction, and the top of ...
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WO/2024/016426A1 |
A method and apparatus for testing a memory chip, a device, and a storage medium. The method comprises: grouping and sequentially enabling a plurality of word lines in a storage array of a memory chip to be tested, wherein a time interva...
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WO/2024/016792A1 |
The present disclosure provides a memory chip anti-miswrite control method and apparatus, and an electrical device. The method comprises: determining whether a main control chip has a write demand on a memory chip; if the main control ch...
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WO/2024/016557A1 |
A shift register circuit and an electronic device, related to the technical field of integrated circuits. The shift register circuit comprises a number m of cascaded flip-flops, clock input terminals of at least some of the flip-flops am...
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WO/2021/194534A9 |
Methods and apparatus for managing power in data storage devices implementing non-volatile memory (NVM) sets are provided. One such apparatus includes a NVM including a first NVM set and a second NVM set, first backend logic circuitry co...
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WO/2024/014081A1 |
The present invention achieves a memory cell in which magnetization can be reversed on the basis of voltage driving without providing a selector element to the memory cell.　This storage device comprises: a memory cell provided with a m...
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WO/2024/011407A1 |
The present disclosure provides a memory cell and a preparation method therefor, a memory, and an information storage method. The memory cell comprises: a piezoelectric substrate layer, a first electrode and a second electrode being resp...
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WO/2024/015046A1 |
In example embodiments described herein are various features for a dual cassette. In one embodiment, a push plate catch and release mechanism is employed that can prevent movement of the push plate when movement of the push plate is not ...
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WO/2024/012375A1 |
The present disclosure provides an MTP memory power supply system and power supply method. A power source voltage generated by a power source is firstly processed by a voltage generator to form a first voltage, and a lifting voltage is t...
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WO/2024/012123A1 |
Provided in the present application are a storage control circuit, a memory, a repair method for the memory, and an electronic device. The storage control circuit is used for controlling a storage array in the memory. The storage array c...
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WO/2024/016015A1 |
A method for fabricating a forming-free resistive random-access memory (RRAM) device is provided. The method includes: fabricating an RRAM cell and annealing the RRAM cell. The RRAM cell includes: a bottom electrode, a switching oxide la...
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WO/2024/011924A1 |
The present disclosure provides a data processing method and apparatus, a memory controller, a device, and a medium. The memory controller which is used for a memory is configured to work in at least one mode comprising a software and ha...
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WO/2024/013604A1 |
Provided is a semiconductor device with a novel configuration. This semiconductor device has: a first computing device that has registers, and a second computing device that has memory circuits, layer selecting circuits, and a computing ...
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WO/2024/014340A1 |
This method for manufacturing a mother glass sheet includes a collection step P2 for collecting a mother glass sheet 8 for inspection, and a measurement step for measuring the shape accuracy of the mother glass sheet 8 for inspection, wh...
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WO/2023/115331A9 |
A shift register, used for a display substrate, the display substrate comprising multiple rows of sub-pixels. The shift register is electrically connected to at least one row of sub-pixels, and is configured to transmit a scanning signal...
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WO/2024/007544A1 |
A memory cell, an array read-write method, a control chip, a memory, and an electronic device, relating to the technical field of semiconductors. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the fi...
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WO/2024/009886A1 |
According to the present invention, an insulating layer has first and second main surfaces. A conductor layer is provided on the first main surface. A metal thin film is provided on the second main surface and has a third main surface fa...
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WO/2024/007378A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system, and a storage apparatus. The data receiving circuit comprises: a first amplification module, which is configured to receive a da...
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WO/2024/010347A1 |
The present technology relates to a high-speed and high-energy-efficiency magnetic tunnel junction element. The high-speed and high-energy-efficiency magnetic tunnel junction element of the present technology comprises: a main pinned lay...
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WO/2024/010988A1 |
Provided is a method and apparatus for digital image watermarking. In the method and apparatus, a computer system receives a first image and receive information for embedding in the first image. The computer system preprocesses the first...
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WO/2024/009384A1 |
A semiconductor device according to an embodiment of the present invention, which is capable of outputting data at high speed despite being relatively inexpensive, is provided with: a plurality of memories that each include a strobe sign...
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WO/2024/007521A1 |
Embodiments of the present disclosure provide a memory and an access method therefor, and an electronic device. The memory comprises at least one memory array, at least one control circuit, and a plurality of read word lines and read bit...
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WO/2024/007543A1 |
Embodiments of the present application provides a storage unit and a memory and a control method therefor. In the storage unit provided by the embodiments of the present application, a first electrode of a first transistor is configured ...
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WO/2024/007363A1 |
Disclosed in embodiments of the present invention are an anti-fuse circuit and a circuit test method. The anti-fuse circuit comprises: a first transistor; and at least one parasitic transistor and at least one parasitic triode which are ...
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WO/2024/010721A1 |
A suspension assembly includes a load beam, a base plate connected to the load beam, and a single actuator disposed in an opening of the base plate. The single actuator is formed of a crystal material that expands along a first axis and ...
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WO/2024/007418A1 |
A memory cell, an NAND string, a memory cell array, and a data access method. The memory cell comprises a first transistor and a second transistor; the first transistor comprises a first electrode, a second electrode, and two independent...
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WO/2024/007377A1 |
Provided in the embodiments of the present disclosure are a data receiving circuit, a data receiving system and a storage apparatus. The data receiving circuit comprises: a first amplification module, comprising: an amplification unit, w...
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WO/2023/184281A9 |
An inspection parameter analysis method and apparatus. The method comprises: acquiring a plurality of groups of first inspection parameters of a product, wherein the first inspection parameters comprise inspection parameters of a plurali...
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WO/2024/007360A1 |
Disclosed in the embodiments of the present disclosure are an anti-fuse unit structure, an anti-fuse array and an operation method therefor, and a memory. The anti-fuse unit structure comprises: a first anti-fuse transistor, which has a ...
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WO/2024/007914A1 |
The present application discloses an SRAM control system, a method, an FPGA chip, and electronic equipment. The SRAM control system comprises a main control module, at least one SRAM control module, and a bus module, the bus module being...
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WO/2024/007391A1 |
A data transmission structure, a data transmission method, and a memory, relating to the field of semiconductor circuit design. The data transmission structure comprises: a data transmission module (100) configured to generate second dat...
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WO/2024/007399A1 |
A memory (10), a control apparatus, a clock processing method, and an electronic device. A clock processing circuit (20) in the memory (10) comprises: a duty ratio module (21), which is configured to adjust the duty ratio of a data clock...
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WO/2024/009665A1 |
This servo pattern recording head comprises a plurality of magnetically separated head cores, and a plurality of gap patterns that are respectively formed on surfaces of the plurality of head cores and record a plurality of servo pattern...
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WO/2024/007398A1 |
A control apparatus (10), a memory (20), a signal processing method, and an electronic device (50). The control apparatus (10) comprises: a receiving module (11), which is configured to receive a read clock signal from a memory, and outp...
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WO/2024/001405A1 |
Disclosed in the embodiments of the present application are an audio processing method and apparatus, and a chip, an electronic device and a storage medium. The method is applied to an electronic device, and the method comprises: perform...
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WO/2024/000811A1 |
Disclosed in the embodiments of the present disclosure are a clock control circuit and a semiconductor memory. The clock control circuit comprises a first decoding path, a second decoding path and a clock gating circuit, wherein the firs...
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WO/2024/001332A1 |
Provided in the present application are a multi-port memory, and a reading and writing method and apparatus for a multi-port memory. The multi-port memory comprises N write ports, one write controller, K write buffers and one memory bloc...
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WO/2024/005932A1 |
The present disclosure generally relates to spin-orbit torque (SOT) devices comprising a bismuth antimony (BiSb) layer. The SOT devices further comprise one or more GeXNiFe layers, where at least one GeXNiFe layer is disposed in contact ...
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WO/2024/006026A1 |
A phonograph record player including a speaker enclosure within the record player that is mechanically insulated from the phonograph components to reduce vibrations from the speakers to the phonograph components. One or more coupling mec...
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WO/2024/000462A1 |
Provided are a display substrate and a display apparatus. The display substrate comprises: a pixel circuit (PE) and a scanning drive circuit, wherein the pixel circuit comprises: a writing transistor and a scan signal line (GL), the scan...
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WO/2024/000910A1 |
A data input verification method and a data input verification structure. The data input verification method comprises: generating a randomly combined input character string (101); on the basis of the input character string and an analog...
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WO/2024/006302A2 |
A semiconductor device includes a floating gate that can be charged in a nonvolatile manner. The floating gate is also structured as an optical waveguide, and may be optically coupled to a photonic circuit, such as an interferometer.
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WO/2024/000630A1 |
The present disclose provides a sense amplifier and a semiconductor memory. The sense amplifier comprises: a power source module, which is provided with an output end, and is used for acquiring temperature data of the power source module...
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WO/2024/000640A1 |
Provided in the present disclosure are a sense amplifier and a semiconductor memory. The sense amplifier comprises a control module provided with an input end and an output end and an amplification module. The control module is configure...
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