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WO/2024/040758A1 |
The present disclosure relates to the technical field of semiconductor circuit design, and provides a voltage generation circuit and a memory. The voltage generation circuit comprises: a voltage output module, configured to receive a ref...
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WO/2024/041048A1 |
A semiconductor device includes a ferroelectric random-access memory (FeRAM) cell. The FeRAM includes a ferroelectric dielectric that is annealed to attain its ferroelectric phase by an induced current flow and heating process. The curre...
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WO/2024/040694A1 |
The present disclosure relates to the technical field of semiconductors and provides a memory and a memory system thereof. The memory comprises storage blocks and a plurality of bit lines corresponding to the same storage blocks; sense a...
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WO/2024/040693A1 |
The embodiments of the present disclosure provide a delay-locked loop and a memory. The delay-locked loop comprises: a preprocessing module, which is configured to receive an initial clock signal, preprocess the initial clock signal, and...
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WO/2024/042386A1 |
Provided are a tape guide roller and tape drive having a guide roller having magnets and bushings to stabilize a roller barrel for a tape medium. The tape guide roller has a roller barrel extending around a vertical axis. The tape medium...
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WO/2024/040432A1 |
Provided in the embodiments of the present disclosure are a display panel, a display device, and a control method for a display panel. The display panel comprises: a base substrate; a plurality of sub-pixels; a plurality of gate lines, w...
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WO/2024/044377A1 |
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel p...
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WO/2024/040699A1 |
Disclosed in the present application are a spin-wave-unit-based in-memory computing array structure and a control method therefor, which relate to the field of integrated circuits. The spin-wave-unit-based in-memory computing array struc...
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WO/2024/044056A1 |
One example includes an integrated circuit (100) with a sense amplifier (105) that includes a first inverter (110) having a first positive power terminal, a first input and a first output; and a second inverter (115) having a second posi...
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WO/2024/040569A1 |
Methods, systems, and devices for data handling during a reflow operation are described. The method may include a memory system receiving first signaling indicating that a reflow operation is to be performed on the memory system and dete...
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WO/2024/040926A1 |
The present invention provides a storage array, and an interconnection structure thereof and an operation method therefor. The storage array comprises: a plurality of bit lines, wherein one row is provided with two bit lines, comprising ...
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WO/2024/036881A1 |
The present invention belongs to the technical field of testing or measurement of semiconductor devices in a manufacturing or processing process. Disclosed are a reconfigurable MBIST method based on an adaptive March algorithm. An adapti...
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WO/2024/036796A1 |
A write leveling circuit applied to a memory, and a control method and control apparatus for the write leveling circuit. The write leveling circuit comprises: a write signal generation unit (21), which is configured to perform delay proc...
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WO/2024/039417A1 |
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and sacrificial layers t...
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WO/2024/037097A1 |
The present application relates to the technical field of storage, and provides a ferroelectric memory and a terminal, which can improve the strength and reading efficiency of a read signal in a reading phase, and reduce the area of the ...
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WO/2024/039431A1 |
Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines i...
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WO/2024/036719A1 |
Embodiments of the present disclosure provide a data receiving circuit and a memory. The circuit comprises: a voltage generation circuit configured to output a first reference voltage signal and a second reference voltage signal in a fir...
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WO/2024/039440A1 |
A lubricant adheres to a magnetic recording medium via at least one of chemisorption or bonding, and contains a perfluorinated polyether attached to or terminated with a functional group that is phosphonic acid, silanol or carboxylic aci...
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WO/2024/037524A1 |
Embodiments of present invention provide a phase change memory (PCM) device. The PCM device includes a first PCM cell with the first PCM cell including an L-shaped phase change element, the L-shaped phase change element having a horizont...
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WO/2024/039486A1 |
An effect known as "rowhammer" may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window...
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WO/2024/036725A1 |
Embodiments of the present invention provide a monitoring circuit and a storage system. The monitoring circuit comprises a voltage detection module and a logic circuit module. The voltage detection module is configured to: detect whether...
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WO/2024/039592A1 |
Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory chip is disclosed. The IC memory chip includes clock receive circuitry to receive a clock signal and...
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WO/2024/037525A1 |
A ferroelectric random-access memory (FeRAM) cell (10) is provided. The FeRAM cell (10) includes a vertical channel (310) between a bottom source/drain region and a top source/drain region (630); a gate oxide (320) surrounding the vertic...
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WO/2024/038786A1 |
Provided are a magnetic recording medium and a magnetic recording cartridge. An average thickness of the magnetic recording medium tT is tT ≦ 5.3 μm, a ratio (A2/A1) of an average creep slope A2 at a temperature of 32 °C and a humidi...
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WO/2024/036876A1 |
Disclosed in the embodiments of the present disclosure is a memory. The memory comprises at least one array area, the array area comprising a storage body area, a first latch area and a second latch area, wherein the first latch area is ...
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WO/2024/036724A1 |
A storage system and an electronic device, which relate to the technical field of semiconductors. The system comprises: a substrate (11); a memory controller (12) arranged on the substrate (11); and a memory module (13) arranged on the s...
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WO/2024/036827A1 |
Embodiments of the present application provide a memory and a manufacturing method therefor, and a read-write control method. In the memory provided in the embodiments of the present application, one source line is provided to electrical...
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WO/2024/036828A1 |
Provided in the embodiments of the present application are a memory and a manufacturing method and a read-write control method therefor. In the memory provided in the embodiments of the present application, a transistor of a storage unit...
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WO/2024/036720A1 |
Provided in the present disclosure are a method for acquiring a row hammer refresh address, and a device. The method comprises: acquiring the current sampling address after a previous row hammer refresh signal arrives; determining whethe...
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WO/2024/038676A1 |
Data held in a volatile storage unit can be stored in a resistance changing element without interposing a transistor of the volatile storage unit. This storage device comprises: a volatile storage unit provided with a volatile storage ...
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WO/2024/036797A1 |
A write leveling circuit applied to a memory, and a control method for the write leveling circuit. The write leveling circuit comprises: a write signal generation unit, which is used for receiving a first clock signal and a first indicat...
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WO/2024/038981A1 |
Disclosed is a memory device including a memory cell storing data by operations of word lines and bit lines. The memory device comprises: switches that form word lines and bit lines in rows and columns and are connected to the word lines...
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WO/2023/018893A9 |
The disclosure is directed to systems, devices, and methods for generating, stabilizing, and controlling mesoscopic spin order of electrons. The device includes a two-dimensional (2D) semiconductor monolayer configured to accommodate a 2...
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WO/2024/038126A1 |
The invention relates to a device for continuously replicating a hologram comprising a coating module which is designed to coat a liquid photopolymer onto a first carrier film, a lamination module which is designed to apply a second carr...
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WO/2024/040107A1 |
A quantum computing system including a quantum computing resource having a plurality of logical qubits, a classical memory, an on-chip decoder controller, and at least one classical processor is disclosed. The on-chip decoder controller ...
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WO/2024/037711A1 |
The present invention relates to a compact writing and reading head for hyper-speed data recording on ceramic material.
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WO/2024/038825A1 |
Provided is a magnetic recording medium capable of improving electromagnetic conversion characteristics. This magnetic recording medium has a tape shape and comprises a recording layer having a granular structure. The magnetic recordin...
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WO/2024/036723A1 |
Provided in the present disclosure are a counting circuit and a memory. The counting circuit comprises a counting module, which is used for outputting a count value when the count value exceeds a preset threshold value; a decoding module...
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WO/2024/035534A1 |
Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a...
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WO/2024/031952A1 |
Disclosed in the present invention are an FRAM reading method and reading circuit. The method comprises: with regard to voltage signals on bit lines of a storage unit and a reference unit in an FRAM array, converting change rates of both...
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WO/2024/031776A1 |
Embodiments of the present disclosure provide a delay-locked loop, a delay locking method, a clock synchronization circuit, and a memory. The delay-locked loop comprises: a frequency division module configured to receive an input clock s...
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WO/2024/034734A1 |
The present invention relates to a NAF memory device in which a NAND flash memory and a flip-flop are coupled together, and an operating method thereof, wherein, by configuring a NAF memory in which a flip-flop is fused to a NAND memory ...
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WO/2024/031815A1 |
Provided in the present disclosure are a sense amplifier, a control method and a semiconductor memory. The sense amplifier comprises a sensing module and an equalization module, the sensing module being connected to a bit line and a comp...
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WO/2024/032122A1 |
Embodiments of the present application provide a memory cell and a fabrication method, a dynamic memory, a storage device, and a read-write method. The memory cell comprises a transistor and a storage capacitor. The transistor comprises ...
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WO/2024/031814A1 |
The present disclosure provides a sense amplifier, a control method, and a semiconductor memory. The sense amplifier comprises a sensing module and an equalization module. The sensing module is connected to a bit line and a complementary...
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WO/2024/032123A1 |
Provided in the embodiments of the present application are a memory cell and a manufacturing method therefor, and a dynamic memory, a storage apparatus and a read-write method. In the memory cell, a source electrode, a drain electrode, a...
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WO/2024/035480A1 |
Technology is disclosed herein for detecting leaky word lines in a non-volatile storage system. The exact leaky word line may be located very rapidly using a divide and conquer approach. Fist a determination may be made whether at least ...
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WO/2024/034492A1 |
Provided is a non-alkali glass plate having a sufficiently high strain point and Young's modulus together with excellent productivity. A non-alkali glass plate according to the present invention is characterized by having a glass composi...
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WO/2024/035476A1 |
Non-volatile memory cells are programmed by pre-charging channels of unselected non-volatile memory cells connected to a selected data word line, boosting the channels of unselected non-volatile memory cells connected to the selected dat...
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WO/2024/032560A1 |
Provided in the present application are a method for over-erase repair of a non-volatile memory, a storage apparatus that can execute the method, and a computer-readable medium storing an instruction for executing the method, wherein the...
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