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Title:
WRITE LEVELING CIRCUIT APPLIED TO MEMORY, AND CONTROL METHOD AND CONTROL APPARATUS FOR WRITE LEVELING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2024/036796
Kind Code:
A1
Abstract:
A write leveling circuit applied to a memory, and a control method and control apparatus for the write leveling circuit. The write leveling circuit comprises: a write signal generation unit (21), which is configured to perform delay processing on a first write signal according to a received first clock signal and output a second write signal; a delay unit (22), which is configured to perform delay processing on a received first data strobe signal and output a second data strobe signal; and a sampling unit (23), which is respectively connected to the delay unit (22) and the write signal generation unit (21), and is configured to output a first sampling signal according to the received second data strobe signal and second write signal, wherein the sampling unit (23) is further configured to receive the first data strobe signal, and output a second sampling signal according to the first data strobe signal and the second write signal. Thus, a controller externally corresponding to the memory can receive the first sampling signal and the second sampling signal, which are output from the write leveling circuit, and the signals sent by the controller to the memory are adjusted, so that the memory can correctly write data.

Inventors:
ZHANG ZHIQIANG (CN)
TANG YULING (CN)
Application Number:
PCT/CN2022/132673
Publication Date:
February 22, 2024
Filing Date:
November 17, 2022
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/4063
Foreign References:
CN208954638U2019-06-07
CN102610268A2012-07-25
CN113615088A2021-11-05
CN208208341U2018-12-07
US20120113728A12012-05-10
CN202210982417A2022-08-16
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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