| Document |
Document Title |
|
WO/2024/000651A1 |
The embodiments of the present disclosure relate to the field of semiconductors. Provided are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, which comprises first active...
|
|
WO/2024/000618A1 |
Embodiments of the present disclosure provide a memory cell detection method and a device. The method comprises: writing first data to a memory cell; performing first reading on the memory cell, so as to adjust a first voltage of a first...
|
|
WO/2024/000617A1 |
The present disclosure provides a sense amplifier and a semiconductor memory. The sense amplifier comprises: a control module, provided with an input end and an output end, and used for obtaining temperature data of an amplifier module, ...
|
|
WO/2024/001622A1 |
The present application provides a ferroelectric memory, and a reading circuit and method for the ferroelectric memory, wherein the reading circuit comprises a first switching transistor, a second switching transistor, an equalizer and a...
|
|
WO/2024/000646A1 |
Provided in the embodiments of the present disclosure is a semiconductor memory, comprising: an input module, which is configured to receive an address/command input signal; a plurality of redundant modules, which are divided into N sets...
|
|
WO/2024/000625A1 |
Provided in the embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises: a first active region; a first gate, located above the first active region, the first active region ...
|
|
WO/2024/005943A1 |
In an implementation, a software application on a computing device directs the device to extract audio data from a media file comprising the audio data and video data, generate a trim proposal based on analysis of speech in the audio dat...
|
|
WO/2023/225772A9 |
The present invention relates to the technical field of integrated circuit testing. Provided are a fully automatic method and system for testing read and write functions of a DRAM storage cell. The method comprises the following steps: a...
|
|
WO/2024/001574A1 |
Provided in the embodiments of the present application is a memory. The memory comprises: a first storage unit, a sensitive amplifier, a first bit line, a second bit line, a first isolator, a second isolator, a third isolator, a fourth i...
|
|
WO/2024/005806A1 |
Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an "angled transistor" if a longitudinal axis of an elongated semiconductor structure...
|
|
WO/2024/005927A1 |
Various illustrative aspects are directed to a data storage device, comprising one or more disks; at least one actuator mechanism configured to position at least a first head proximate to a first disk surface and a second head proximate ...
|
|
WO/2024/001328A1 |
The present application relates to the field of flash-based FPGAs, and discloses a program disturb suppressing configuration control circuit of a flash-based FPGA. Compared with conventional configuration control circuits, in this config...
|
|
WO/2024/006010A1 |
In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affe...
|
|
WO/2024/006848A1 |
An integrated current sensing amplifier with offset cancellation implemented in GaN technology. The current sensing amplifier senses the current flowing through a low side power FET or a high side power FET of a half bridge circuit. The ...
|
|
WO/2024/005140A1 |
The present invention provides a compound which is represented by formula (1). (In the formula, A represents a polymerizable group; n represents an integer of 1 to 3; L represents an optionally branched linking group having a valence o...
|
|
WO/2024/004126A1 |
This domain wall displacement element comprises a first magnetoresistance effect element and a first transistor. A first domain displacement layer of the first domain displacement layer is electrically connected to the first active regio...
|
|
WO/2024/006148A1 |
A memory includes a link training circuit with a pseudo-random bit sequence (PRBS) generator and a burst error detection counter. The burst error detection counter including a comparator, a first input coupled to the data input, a second...
|
|
WO/2024/001894A1 |
Disclosed in the present application is an information verification method. The method comprises: acquiring a fluorescence signal, wherein the fluorescence signal is an electrical signal, which is generated on the basis of a plurality of...
|
|
WO/2024/001703A1 |
Embodiments of the present disclosure relate to a memory apparatus. The memory apparatus comprises: a printed circuit board; an interposer arranged on the printed circuit board; a memory cell group arranged on the interposer; a control u...
|
|
WO/2024/005923A1 |
The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second B...
|
|
WO/2024/005141A1 |
The present invention provides a composition for holographic recording media, the composition being characterized by containing the components (a) to (d) described below, and being also characterized in that the abundance of allophanate ...
|
|
WO/2024/000324A1 |
Some embodiments of the present application relate to the technical field of semiconductors. Provided are a ferroelectric memory array and a preparation method therefor, and a memory and an electronic device, which aim to improve the the...
|
|
WO/2024/000628A1 |
The present disclosure provides a sense amplifier and a semiconductor memory. The sense amplifier comprises: a control module which is provided with an input end and an output end and is used for obtaining temperature data of a writing m...
|
|
WO/2024/005139A1 |
Provided is a method for producing an optical element, wherein a holographic recording medium having a recording layer containing a polymerizable compound and a photopolymerization initiator is subjected to multiple hologram-recording ex...
|
|
WO/2024/000629A1 |
Provided in the present disclosure are a sense amplifier and a semiconductor memory. The sense amplifier comprises a control module, which is provided with an input end and a first output end and is used for acquiring temperature data of...
|
|
WO/2023/249718A1 |
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected word lines. The memory cells are disposed in strings and configured to retain a threshold voltage. A control means is configured to ap...
|
|
WO/2023/246931A1 |
A memory device, a memory system, and a method thereof are provided. In the method, an N-th programming pulse is applied to a word line coupled to memory cells of the memory device each with a target programming state being an i-th progr...
|
|
WO/2023/245923A1 |
The present disclosure provides a memory device and a ZQ calibration method. The memory device comprises: a master chip and a plurality of slave chips, the master chip and the slave chips being each provided with a first transmission end...
|
|
WO/2023/245792A1 |
Embodiments of the present disclosure provide a refresh control circuit and a method therefor, and a memory. The refresh control circuit comprises: an address output module, configured to output an address to be refreshed signal, the add...
|
|
WO/2023/245746A1 |
The embodiments of the present disclosure relate to a word line drive circuit, a word line driver, and a storage apparatus. The word line drive circuit comprises: at least two sub-word line drivers, wherein each sub-word line driver is c...
|
|
WO/2023/247554A1 |
The invention relates in a first aspect to a master plate for industrial hologram replication, comprising a flat and planar composite pane having a thick glass pane as a carrier for minimizing the deflection of the master plate and a thi...
|
|
WO/2023/245747A1 |
Embodiments of the present disclosure relate to a word-line driver and a storage apparatus. The word-line driver comprises: a PMOS region, comprising first active regions extending in a first direction, wherein each of the first active r...
|
|
WO/2023/249721A1 |
An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logi...
|
|
WO/2023/245921A1 |
Provided in the present disclosure are a memory device and a ZQ calibration method. The memory device comprises: two calibration resistor interfaces, which are connected to the same ZQ calibration resistor; a first master chip, a plurali...
|
|
WO/2023/248080A1 |
The invention concerns a method for characterizing a magnetic device including a plurality of binary nanomagnets, which may be arranged in an array, comprising (i) providing a magnetic device, which is a binary nanomagnetic array, compri...
|
|
WO/2023/250030A1 |
Technologies and implementations for a voltage management circuit. The voltage management circuit may be configured to facilitate management of behavior of electronic devices including management of process corners associated with semico...
|
|
WO/2023/247553A1 |
The invention relates to a magnetic card (2) reader (1), which comprises: - an electronic card (5); - a magnetic reading head (6) which is intended to read data contained in a magnetic strip (9) of a magnetic card and to transmit these d...
|
|
WO/2023/098927A9 |
The present disclosure provides a display substrate and a display apparatus. The display substrate comprises: a base substrate, comprising a display area and a peripheral area located on at least one side of the display area; a pixel arr...
|
|
WO/2023/245780A1 |
Embodiments of the present disclosure relate to the field of semiconductor testing, and in particular to a test method, a test structure, and a memory. The test structure comprises: an instruction storage unit used for storing a test com...
|
|
WO/2023/245728A1 |
The present disclosure provides a semiconductor structure and a manufacturing method therefor, a memory and an operation method therefor. The semiconductor structure comprises: a substrate, the substrate having a plurality of active regi...
|
|
WO/2023/248415A1 |
A memory device in which, in a plan view on a substrate, a page is configured from a plurality of memory cells arranged in a row direction, and a plurality of pages are arranged in a column direction, the memory device being characterize...
|
|
WO/2023/246057A1 |
A linear motor driving method and device, and a storage medium. The method comprises: obtaining a time domain audio waveform for driving the audio data of the linear motor and a working frequency of the linear motor to be driven; process...
|
|
WO/2023/247645A1 |
An example one-time programmable (OTP) memory device is provided. The OTP memory device include a passivation layer. A top metal layer is positioned below the passivation layer. The top metal layer includes one or more holes configured t...
|
|
WO/2023/245667A1 |
Provided are a shift register unit, a gate driving circuit, a display apparatus, and a driving method. The shift register unit comprises: a first control circuit (01), which is configured to control signals of a first node (N1) and a sec...
|
|
WO/2023/245751A1 |
Embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a storage device. The data receiving circuit comprises: a first amplification module configured to receive a data signal, a first refere...
|
|
WO/2023/249717A1 |
The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared b...
|
|
WO/2023/207216A9 |
A shift register (ASG), a gate drive circuit (141), a display panel (10) and an electronic device. The shift register (ASG) comprises: a node control module (142), which is electrically connected to a first level signal receiving end (VG...
|
|
WO/2023/245942A1 |
An SSD finite window data deduplication identification method and apparatus, a computer device, and a storage medium. The method comprises: if a command is a write command, allocating a write buffer area and receiving data from a host, d...
|
|
WO/2023/249738A1 |
Computer memory arrays employing memory banks and integrated serializer/de-serializer circuits for supporting serialization/de-serialization of read/write data in burst read/write modes, and related methods are disclosed. The memory arra...
|
|
WO/2023/250032A1 |
Technologies and implementations for a wake-up circuit. The wake-up circuit may be configured to reduce a peak value of current draw during waking up of an electronic device. The reduction of the peak value of current draw facilitates a ...
|
