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WO/2023/201883A1 |
A memory failure test method, a memory failure test apparatus, a computer-readable storage medium, and an electronic device, relating to the technical field of integrated circuits. The memory failure test method comprises: executing a da...
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WO/2023/200468A1 |
A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, sc...
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WO/2023/197399A1 |
Disclosed are a memory testing method and apparatus, and a memory system. The method comprises: executing a write operation and a read operation on a memory unit in a noise environment, wherein the write operation comprises writing test ...
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WO/2023/199182A1 |
Provided is a novel semiconductor device. The semiconductor device comprises a first cache, a second cache, a cache controller, and cores, wherein the cache controller has a function that causes data for performing program processing to ...
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WO/2023/197678A1 |
Disclosed in the embodiments of the present application are an information recording method and apparatus, and an electronic device and a storage medium. The method comprises: during a running process of a playing program, in response to...
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WO/2023/200733A1 |
Examples of a load beam are provided. The load beam includes a base portion with an opening at a distal end. The opening is configured to receive a heat assisted magnetic recording (HAMR) head slider extending therethrough. The load beam...
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WO/2023/200767A1 |
In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold sw...
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WO/2023/198189A1 |
Disclosed are a memory error prediction method and apparatus, and a device, which relate to the field of computers. After memory error data is acquired, on the basis of spatial-temporal information that reflects a memory error, and a phy...
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WO/2023/199796A1 |
Provided is an electronic device that enables a reduction in dust or the like that adheres to a ventilation region of a heat-generating component or a heat-dissipating component. An electronic device (10) has: a power supply unit (40); a...
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WO/2023/197767A1 |
A ferroelectric memory (100). A first storage unit in the ferroelectric memory (100) comprises a transistor and a plurality of capacitors; first electrode plates of the plurality of capacitors are connected to a drain of the transistor; ...
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WO/2023/199474A1 |
This memory device comprises a page made of a plurality of memory cells arranged in columns, in plan view, on a substrate, wherein, during a page erase operation, voltages to be applied to a first impurity layer, a second impurity layer,...
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WO/2023/197389A1 |
A neuron device (10) based on a magnetic tunnel junction, and a neural network apparatus. The neuron device (10) based on a magnetic tunnel junction comprises: a synthetic antiferromagnetic structure layer (111), wherein a bottom electro...
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WO/2023/197774A1 |
A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of ...
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WO/2023/195230A1 |
Power consumption is reduced in a semiconductor integrated circuit that retains setting information in a memory. The semiconductor integrated circuit comprises a long-term retention memory and a short-term retention memory. Among these...
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WO/2023/196000A1 |
Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog inputs. In one example, a system comprises a vector by matrix multiplication array comprising a plural...
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WO/2023/195585A1 |
The present invention relates to a bit line sense amplifier for sensing and amplifying a voltage of a bit line. The bit line sense amplifier comprises: a first inverter (121) having an input end connected to a positive bit line (BLT) and...
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WO/2023/193587A1 |
The present application relates to a signal processing method for a storage system interface circuit. The signal processing method comprises: preprocessing a received signal to obtain an input signal; removing a weighted feedback signal ...
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WO/2023/193340A1 |
A semiconductor memory (10), a refreshing method, and an electronic device (50). The semiconductor memory (10) comprises a main storage area (11) and a flag storage area (12). A plurality of storage rows (111-1, 111-2) are provided in th...
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WO/2023/193588A1 |
The present application relates to a signal processing method for a storage system interface circuit, comprising: preprocessing a received signal to obtain an input signal; removing a weighted feedback signal in the input signal to obtai...
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WO/2023/195999A1 |
Numerous examples are disclosed of an artificial neural network comprising a plurality of reference arrays used for configuration of a vector-by-matrix multiplication array. In one example, a system comprises a vector-by-matrix multiplic...
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WO/2023/193336A1 |
A semiconductor memory (10), a refresh method, a control method, and an electronic device. The semiconductor memory (10) comprises a main storage area (11) and a mark storage area (12); a plurality of storage groups (111-1, 111-2) are pr...
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WO/2023/196317A1 |
A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be ba...
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WO/2023/196002A1 |
Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs. In one example, a system comprises a vector by matrix multiplication array comprising a plura...
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WO/2023/193337A1 |
The present disclosure provides a semiconductor structure layout, comprising: an active area pattern; a first-type gate pattern overlapping with the active area pattern, and extending along a first direction; and a metal layer pattern ex...
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WO/2023/193545A1 |
A power-failure protection method and apparatus for a chip, and a chip and a storage medium. The power-failure protection method for a chip comprises: collecting an internal reference voltage AD value of a chip by means of an AD collecti...
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WO/2023/193738A1 |
The embodiments of the present application disclose a manufacturing method for a magnetic memory, the method comprising: etching laminated layers of a magnetic tunnel junction until a metal layer is reached; oxidizing or nitriding the me...
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WO/2023/189347A1 |
The primary purpose of the present invention is to provide a magnetic recording medium having excellent electromagnetic conversion characteristics. The present technology provides a magnetic recording medium having a layered structure in...
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WO/2023/190146A1 |
This memory circuit (11) comprises: first switches (SW) which are provided for each group of a first bit line (BL1) and a second bit line (BL2) and are connected to a first memory cell (MC1) and a second memory cell (MC2); an all first b...
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WO/2023/183977A1 |
The present invention relates to a computer-implemented system and method for providing streams and playbacks of video and audio recordings in respect of artist performances before live audiences. In particular, the invention relates to ...
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WO/2023/187132A1 |
Disclosed is a device for recording data in nucleic acids. The device comprises a liquid dispenser configured to dispense a carrier drop, a drop collecting element, wherein during operation of the device the carrier drop flies from the l...
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WO/2023/187420A1 |
A memory including: an array of memory cells; a memory access logic programmable to generate a write allocation that maps an input comprising elements of data in a first sequence to the memory cells of the array and a read allocation tha...
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WO/2023/192964A1 |
Leveraging stochastic physical characteristics of resistive switching devices to generate data having very low cross correlation among bits of that data is disclosed. Data generated from stochastic physical characteristics can also be re...
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WO/2023/184705A1 |
The present disclosure provides a data transmission circuit and method, and a storage device. The data transmission circuit comprises a mode register data processing module, an external data transmission module and an internal data trans...
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WO/2023/192733A1 |
The present disclosure generally relates to a magnetic recording head for a magnetic media drive. The magnetic recording head comprises a near field transducer (NFT), a vertical cavity surface emitting laser (VCSEL) device, and a wavegui...
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WO/2023/189233A1 |
An object of the present invention to provide a magnetic disk that is flat while being thin, and is resistant to physical errors. The present invention provides a magnetic disk having a hole in the center, wherein the disk thickness is...
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WO/2023/192965A1 |
Improved differential programming of multiple two-terminal memory cells that define an identifier bit is provided. Differential programming can apply a program cycle to multiple memory cells concurrently, detect a program event for one (...
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WO/2023/192966A1 |
Configurable and reconfigurable solid state electronic devices for performing matrix multiplication are provided. The solid state electronic devices at least in part utilize a resistive non-volatile memory circuit for storing data states...
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WO/2023/191711A1 |
Embodiments of the disclosure provide a device-cloud collaboration-based image processing method and apparatus, an electronic device, a storage medium, a computer program product and a computer program. The method comprises: by means of ...
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WO/2023/191935A1 |
Systems, methods, and a computer-readable medium are provided for matching textless elements to texted elements in video content. A video processing system including a textless matching system may divide a video into shots, identify shot...
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WO/2023/187782A1 |
Apparatus including a plurality of non-volatile memory cells of variable resistance organized to perform an instant analog approximation for a reliable neural network inference, by a current distribution governed by conductivity of the c...
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WO/2023/186492A1 |
An apparatus includes a SRAM memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, co...
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WO/2023/184720A1 |
An antifuse address decoding circuit, an operation method, and a memory. The antifuse address decoding circuit comprises: a pre-decoding module (10), configured to decode a programming address of an antifuse storage array and output a pr...
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WO/2023/191919A1 |
Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller det...
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WO/2023/187133A1 |
In the present disclosure, various devices and methods covering a technology for combinatorial liquid handling are disclosed. At least some example embodiments of the devices disclosed herein may include a plurality of liquid dispensers ...
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WO/2023/184707A1 |
Embodiments of the present invention provide a memory and a manufacturing method therefor, and an electronic device. The memory comprises a substrate, and a word line, a bit line and a storage unit on one side of the substrate. The stora...
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WO/2023/190541A1 |
Provided is a magnetic recording medium capable of reducing surface dynamic friction of a magnetic layer and achieving good electromagnetic conversion characteristics. This magnetic recording medium is a tape-like magnetic recording me...
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WO/2023/188634A1 |
PROBLEM TO BE SOLVED: To provide a dielectric reproduction device and a dielectric recording and reproduction device that can increase reproduction speed. SOLUTION: A detection means 11 is provided so as to be able to perform a scan rela...
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WO/2023/192795A1 |
An apparatus and system are described to provide an in-memory computing non-volatile flash memory cell array used in a neural network. Each cell includes a Resistive RAM memory (RRAM) and a physical resistor formed from a high resistive ...
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WO/2023/192234A1 |
A hard disk drive enclosure base includes a non-uniform disk shroud surface extending from a top to a floor, the shroud surface including a first portion having a first radius and clearance along the circumference of the shroud surface a...
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WO/2023/192032A1 |
A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.
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