Title:
POWER-FAILURE PROTECTION METHOD AND APPARATUS FOR CHIP, AND CHIP AND STORAGE MEDIUM
Document Type and Number:
WIPO Patent Application WO/2023/193545
Kind Code:
A1
Abstract:
A power-failure protection method and apparatus for a chip, and a chip and a storage medium. The power-failure protection method for a chip comprises: collecting an internal reference voltage AD value of a chip by means of an AD collection channel; and when it is determined according to the internal reference voltage AD value that a power supply voltage of the chip is less than a first preset voltage, controlling the chip to execute a power-failure memory operation, and when it is determined according to the internal reference voltage AD value that the power supply voltage of the chip is less than a second preset voltage, controlling the chip to execute a reset operation. Therefore, data in a flash can be prevented from frequent erasing and writing, thereby prolonging the service life of a chip, and reducing the control cost for power-failure protection of the chip.
Inventors:
SHI HAO (CN)
Application Number:
PCT/CN2023/078824
Publication Date:
October 12, 2023
Filing Date:
February 28, 2023
Export Citation:
Assignee:
MR SEMICONDUCTOR LTD (CN)
International Classes:
G11C16/30; G11C16/34
Domestic Patent References:
| WO2017054487A1 | 2017-04-06 |
Foreign References:
| CN114783494A | 2022-07-22 | |||
| CN105807885A | 2016-07-27 | |||
| CN112562764A | 2021-03-26 | |||
| CN110609170A | 2019-12-24 | |||
| CN112134349A | 2020-12-25 | |||
| CN112542204A | 2021-03-23 |
Attorney, Agent or Firm:
BEIJING LISENG INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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