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WO/2023/212879A1 |
Disclosed in embodiments of the present disclosure are an object audio data generation method and apparatus, an electronic device, and a storage medium. The method comprises: obtaining sound data of at least one sound object; obtaining c...
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WO/2023/215382A1 |
A dynamic random access memory (DRAM) device may include an array of DRAM cells, with each DRAM cell configured to store a high logic voltage and a low logic voltage. The DRAM device may further include a precharge circuit configured to ...
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WO/2023/212986A1 |
A test circuit checking method, a test platform (30), a storage medium and a test system (50). The test circuit checking method comprises: sending a control signal to a test circuit (501), and determining a test mode signal, which is out...
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WO/2023/215063A1 |
Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or simi...
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WO/2023/214741A1 |
An audio output system is provided. The audio output system comprises: a key device which includes a communication tag; a main device which stores a first playlist and outputs audio content associated with the communication tag on the ba...
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WO/2023/214739A1 |
An audio output system and method are provided. An audio output system according to some embodiments comprises: an audio output device for outputting different audio contents according to a sound doll; a user terminal for controlling the...
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WO/2023/215052A1 |
Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson...
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WO/2023/213014A1 |
Disclosed are an anti-fuse structure and a manufacturing method therefor, an anti-fuse array and a storage device. The anti-fuse structure comprises: a substrate comprising a first doped region and a second doped region; a first gate and...
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WO/2023/206219A1 |
Provided in the present disclosure are a drive circuit, a drive method, and a display apparatus. The drive circuit comprises a first pull-down node, a first control circuit, and a pull-up node reset circuit, wherein the first control cir...
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WO/2023/206744A1 |
A signal control circuit (10), a signal control method, and a semiconductor memory. The signal control circuit (10) comprises: a generation module (11), used for accumulating the number of times of execution of an activation operation, a...
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WO/2023/211616A1 |
Example systems, computer readable medium and methods include receiving a video taken from a drone where the drone followed a flight path based on a flight plan. A user interface is presented that provides options for the user to select ...
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WO/2023/206748A1 |
The present disclosure provides a data writing method for a memory array, a test method for a memory array, a data writing apparatus for a memory array, a computer readable medium, and an electronic device. The data writing method compri...
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WO/2023/211617A1 |
Example systems, computer readable medium and methods for automatically generating portrait videos from landscape videos include receiving a landscaped video, identifying one or more objects to track, and tracking the one or more objects...
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WO/2023/206749A1 |
A calibration control circuit (10), an electronic device, and a calibration control method. The calibration control circuit (10) comprises an off-chip calibration module (11) and a mode switching module (13), and the off-chip calibration...
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WO/2023/212429A1 |
A storage device reclassification system includes a storage device reclassification subsystem coupled to a storage device that has a NAND storage subsystem and that is configured to perform first storage operations associated with a firs...
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WO/2023/212117A1 |
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells.The control circuit is configured to: acquire a first set of read levels on a wordline of a first block o...
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WO/2023/210382A1 |
In the present invention, a processor acquires a first signal based on a first result of the servo pattern being read by a first servo read element while the first servo read element is located on the reference area of magnetic tape, acq...
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WO/2023/207806A1 |
A shift register, a gate driving circuit and a display apparatus. The shift register comprises a first control module (10), a first output module (20), a second output module (30), a second control module (40), a third control module (50...
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WO/2023/207543A1 |
A media content publishing method and apparatus, and a device, a storage medium and a program product. The method comprises: in response to a publishing page display operation acting on a photographic page, switching the current display ...
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WO/2023/206752A1 |
Disclosed in the embodiments of the present disclosure are a test method and test system for a memory. The method comprises: providing a memory, wherein the memory at least comprises a plurality of first storage units and a plurality of ...
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WO/2023/208571A1 |
A data storage medium (2) comprising a stacked plurality of layers (9), each layer composed of a layer material selected from a group comprising at least two different dielectric materials, adjacent layers being formed of different mater...
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WO/2023/206152A1 |
An anti-fuse memory, for use in increasing a read success rate of the anti-fuse memory. The anti-fuse memory comprises a storage unit, a bit line, a word line, and a write line. The storage unit comprises an active region, and a selectio...
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WO/2023/212568A1 |
An integrated circuit (IC) may include a memory device and a circuit coupled with the memory device. The circuit may precondition the memory device to sustain oscillations, initiate first oscillations in a first loop that includes the me...
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WO/2023/210643A1 |
[Problem] To provide a hardware accelerator processor for full-text search. [Solution] Provided is a full-text search processor comprising: a character storage element in which text data to be searched is temporarily stored such that eac...
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WO/2023/209485A1 |
Provided is a semiconductor device having a small circuit size and reduced power consumption. This semiconductor device includes first to fifth circuits. Each of the first to fourth circuits has first and second cells, a sixth circuit, f...
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WO/2023/207380A1 |
Embodiments of the present application relate to a calibration circuit and method and a related device. The circuit is electrically connected to a ZQ port, and a reference resistor corresponding to the ZQ port is grounded; the circuit co...
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WO/2023/209491A1 |
Provided is a semiconductor device that has a novel structure. The present invention has: a base die that has a clock signal generation circuit and a first synchronization circuit provided thereto; and a plurality of dies that are layere...
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WO/2023/210161A1 |
The present invention inhibits a reduction in the life of a nonvolatile memory in which write processing is performed again when a write operation fails. A memory cell is interposed between a pair of signal lines. A write control circu...
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WO/2023/210388A1 |
The present technology is an information processing device, a method, and a program that facilitate understanding respective parts in a musical piece that respective players are in charge of. The information processing device includes a ...
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WO/2023/208088A1 |
Embodiments of the present application relate to the technical field of electronics. Disclosed are a storage chip, a storage apparatus and an electronic device. The storage chip comprises a plurality of first storage units, and each firs...
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WO/2023/211613A1 |
Systems and methods for adaptive data encoding for memory systems are disclosed. In one aspect, a memory bus replaces a data bus inversion encoding technique with a more flexible encoding scheme which periodically calculates cluster cent...
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WO/2023/208719A1 |
The invention relates to an energy efficient non-volatile cryogenic memory (SUPERTRACK) which comprises - a ferrimagnetic, ferromagnetic or synthetic antiferromagnetic racetrack (RT); and a superconducting shift element in proximity to t...
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WO/2023/209973A1 |
The present invention comprises a plurality of voltage generation circuits (1, 2, 3) which are provided in an environment to be irradiated with neutron rays and which are connected in parallel. Each of the voltage generation circuits com...
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WO/2023/206657A1 |
A test circuit (400), a test method, and a memory. The test circuit (400) comprises: a first integrating circuit (401) used for receiving a first test signal (Test1) and configured to integrate the first test signal (Test1) to output a f...
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WO/2023/211511A1 |
Technologies relating to crossbar array circuits with a 2T1R RRAM cell that includes at least one NMOS transistor and one PMOS transistor for low voltage operations are disclosed. An example apparatus includes a word line; a bit line; a ...
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WO/2023/211532A1 |
Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first l...
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WO/2023/206632A1 |
Disclosed in the embodiments of the present disclosure are a detection circuit for a storage array, a detection method of the detection circuit, and a memory. The detection circuit for a storage array comprises: at least one storage arra...
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WO/2023/206634A1 |
Provided in the embodiments of the present disclosure are a calibration control circuit, an electronic device and a calibration control method. The calibration control circuit comprises: an off-chip calibration module, configured to rece...
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WO/2023/206751A1 |
Embodiments of the present invention provide a calibration control circuit, an electronic device, and a calibration control method. The calibration control circuit comprises: a process module configured to, in a first test mode, perform ...
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WO/2023/204889A1 |
Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap posit...
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WO/2023/204111A1 |
A plurality of SRAM cells (C1) are commonly connected to both a write bitline (WBL, WBLB) extending in a Y-direction and a local read bitline (RBL) extending in the Y-direction. A local amplifier (B1) connected to the local read bitline ...
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WO/2023/204348A1 |
The present invention relates to a smartphone recorder. The smartphone recorder according to an embodiment of the present invention comprises: a case body comprising a front cover attachable to/detachable from the rear surface of a smart...
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WO/2023/203790A1 |
A memory system (1), which is an example of a storage device according to one embodiment of the present disclosure, comprises a magnetoresistive element (120) that has a magnetization direction variable between a first state and a second...
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WO/2023/205322A1 |
A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of ...
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WO/2023/204237A1 |
A magnetic recording medium manufacturing method according to the present invention is a method for manufacturing a magnetic recording medium comprising a substrate, an underlayer, and a perpendicular magnetic layer having an L10 structu...
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WO/2023/203431A1 |
Provided is a semiconductor device that has a small circuit scale and in which power consumption is reduced. The semiconductor device has first to fourth cells, first and second circuits, and first to fourth current generation circuits. ...
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WO/2023/202061A1 |
A nano memory for ultra-high-density data storage, and a preparation method therefor. Donor and acceptor groups are reasonably introduced into an amphiphilic block copolymer, micelles are formed by means of self-assembly to serve as memo...
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WO/2023/203435A1 |
Provided is a semiconductor device having a novel configuration. The semiconductor device includes: a first element layer including a control unit; and a second element layer provided as stacked on the first element layer. The second ele...
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WO/2023/202166A1 |
A bit line reading circuit (201), a memory (1) and an electronic device. In the bit line reading circuit (201), a bit line (BL) is connected to a ferroelectric memory cell (101), and the ferroelectric memory cell (101) comprises n ferroe...
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WO/2023/203512A1 |
Systems and methods for automatically gating a data strobe during a read operation by the DRAM are disclosed. The method includes detecting, and automatically opening the gate when the DQS signal is driven. A system for automatically gat...
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