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WO/2024/054303A1 |
Various embodiments include methods for implementing flexible ranks in a memory system. Embodiments may include receiving, at a memory controller, a first memory access command and a first address at which to implement the first memory a...
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WO/2024/050926A1 |
Embodiments of the present disclosure provide a data processing structure, a semiconductor structure and a memory. The data processing structure comprises a data sampling module, the data sampling module comprises a logic module and a co...
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WO/2024/053014A1 |
This memory device having, on a substrate in a plan view, a plurality of pages which are each formed by a plurality of memory cells arrayed in the row direction and which are arrayed in the column direction is characterized in that: the ...
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WO/2024/051658A1 |
A shift register unit and a display panel. The shift register unit comprises: a first control circuit (10), a second control circuit (20), a third control circuit (30), and an output circuit (40), wherein the first control circuit (10) i...
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WO/2024/054888A1 |
The subject technology receives frames of a source media content. The subject technology detects from the frames of the source media content, a first gesture indicating a cut point at a particular frame of the source media content, the c...
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WO/2024/050905A1 |
Embodiments of the present disclosure provide a mode register setting code generation circuit and method, a circuit and method for setting a mode register, and a memory. The mode register setting code generation circuit comprises: at lea...
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WO/2024/054280A1 |
The present disclosure generally relates to improving adaptive tuning of different clock rates of a memory device. Rather than clock rates only being determined off of one parameter such as workload, the clock rates now will be determine...
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WO/2024/053740A1 |
Provided is a glass for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproducing device that is an amorphous glass that has a B2O3 content of 0.10-2.00 mol% inclusive, a Na2O content of 1...
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WO/2024/053176A1 |
The present invention provides a sputtering target which enables a magnetic layer of a magnetic recording medium to maintain high coercivity, while being capable of improving magnetic separation between magnetic particles. This sputterin...
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WO/2024/053056A1 |
Provided is glass for a magnetic recording medium substrate or for a glass spacer to be used in a magnetic recording/reproduction device, said glass being amorphous glass with a B2O3 content of 0.10-2.00 mol%, a Na2O content of 1.00-6.00...
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WO/2024/053015A1 |
The present invention provides a memory device in which a page is formed from a plurality of memory cells arranged in a row direction and a plurality of pages are arranged in a column direction on a substrate in a plan view. The memory c...
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WO/2024/054317A1 |
Memory stacks having substantially vertical bitlines, and chip packages having the same, are disclosed herein. In one example, a memory stack is provided that includes a first memory IC die and a second memory IC die. The second memory I...
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WO/2024/050689A1 |
A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a periphe...
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WO/2024/053741A1 |
Provided is a glass for a magnetic recording medium substrate, the glass being amorphous glass having a temperature T1 of 1600℃ or lower at a viscosity of 102.0 dPa·s and also having a specific elastic modulus of 34.0 MNm/kg or higher.
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WO/2024/052072A1 |
A track and hold circuit (100) for sampling an input signal, the track and hold circuit (100) comprising a first stage (200) and a second stage (300) and being arranged to operate alternately in a track mode and a hold mode. The first st...
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WO/2024/054316A1 |
Disclosed wherein stacked memory dies that utilize a mix of high and low operational temperature memory and non-volatile based memory dies, and chip packages containing the same. High temperature memory dies, such as those using non-vola...
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WO/2024/054276A1 |
An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The contro...
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WO/2024/054755A2 |
Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configur...
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WO/2024/052256A1 |
The invention relates to a benzopyrylium dyestuff of formula (I), wherein R200,R201, R202, R203, R204, R205, R206, R207 and R208 each independently represent hydrogen, C1- to C16-alkyl, C4- to C7-cycloalkyl C7- to C16-aralkyl, C6- to C10...
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WO/2024/054309A1 |
Mitigating or managing an effect known as "rowhammer" upon a DRAM device may include a memory controller receiving an activation count threshold value from the DRAM device. The memory controller may detect row activation commands directe...
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WO/2024/048955A1 |
According to an embodiment, an electronic device (101) may comprise: at least one microphone (250), at least one speaker (255), a display (160), and at least one processor (120). The at least one processor may be configured to output a r...
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WO/2024/047454A1 |
The present invention provides a highly integrated and reliable semiconductor device. A back gate of a second transistor is electrically connected to a control signal line that provides a control signal for controlling the threshold volt...
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WO/2024/049141A1 |
An electronic device according to one embodiment can identify, from an application processor, a request for encrypting data; encrypt the data on the basis of an ARC included in a mapping table on the basis of the request; acquire, on the...
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WO/2024/046230A1 |
A memory training method, comprising: obtaining training data, and writing the training data into an external memory particle according to an address signal; reading the training data from the external memory particle; obtaining a verifi...
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WO/2024/045263A1 |
Embodiments of the present disclosure provide a control circuit and a semiconductor memory. The control circuit is connected to a sensitive amplification circuit, and the control circuit comprises a pre-charging control module and a powe...
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WO/2024/049531A1 |
To reduce spikes in the current used by a NAND memory die, different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of t...
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WO/2024/045354A1 |
The present disclosure relates to the field of the design of semiconductor circuits. Provided are a clock architecture of a memory, and a memory. The clock architecture of the memory comprises: an on-chip system, which is configured to g...
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WO/2024/049532A1 |
To reduce spikes in the current used by a NAND memory die, different ramp rates are used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in a multi-level cell (MLC) for...
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WO/2024/049524A1 |
An apparatus is provided that includes a block of memory cells having a NAND string that includes a first select transistor, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an eras...
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WO/2024/049732A1 |
A pulse generator circuit (210) includes a charge pump (114) having a charge pump output. A voltage divider (R1/R2) is coupled to the charge pump output. The voltage divider (R1/R2) has a voltage divider output. An error amplifier (116) ...
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WO/2024/045262A1 |
Disclosed in embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises: a plurality of active regions; a bit line selection unit, comprising a first gate, a second gate, a thi...
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WO/2024/049533A1 |
To reduce spikes in the current used by a NAND memory die during a write operation using smart verify, different amounts of delay are introduced into the loops of the programing algorithm. Depending on the number of verify levels followi...
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WO/2024/049750A1 |
A control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. Rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. Row...
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WO/2024/045218A1 |
The present disclosure relates to the field of semiconductor circuit design, and in particular to a monitoring circuit, a refreshing method, and a memory. The monitoring circuit comprises: a sampling module for sampling an initial addres...
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WO/2024/049529A1 |
Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected...
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WO/2024/045733A1 |
A semiconductor structure manufacturing method, a semiconductor structure and a semiconductor device. The method comprises: providing a substrate (1), and separately forming on the substrate (1) a bit line structure (210), a capacitor st...
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WO/2024/045219A1 |
The present disclosure relates to the field of semiconductor circuit designs, and particularly relates to a monitoring circuit, a refreshing method, and a memory. The monitoring circuit comprises: a sampling module, which samples an init...
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WO/2024/045264A1 |
Disclosed in the embodiments of the present disclosure are a semiconductor structure and a memory. The semiconductor structure comprises at least one sub-wordline driver, wherein the sub-wordline driver comprises: a plurality of first ac...
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WO/2024/049683A1 |
A memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data widths (i.e., number of data signals) allocated to each channel are configurable such that a given group of data input/output (I/O) sign...
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WO/2024/045260A1 |
The present disclosure relates to the field of semiconductor circuit design, in particular to a monitoring circuit, a refreshing method, and a memory. The monitoring circuit comprises: a sampling module for sampling an initial address to...
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WO/2024/050265A1 |
A memory device enables write operations with an extended write data window. In a first type of write operation, the memory device receives a merged row/column command at an input interface. The memory device initiates a row operation (e...
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WO/2024/049542A1 |
Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization...
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WO/2024/049715A1 |
An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can ...
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WO/2024/045113A1 |
A method includes assigning a respective initial credit value to each LUN of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a u...
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WO/2024/045267A1 |
A sense amplifier (100) control method (200) and an electronic device using the control method. The sense amplifier (100) control method (200) comprises, according to a time sequence, an idle stage, an offset cancellation stage, a charge...
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WO/2024/041748A1 |
A connector (100, 102) is provided for generating a biological structure (400, 500, 600, 700) comprising: a protein backbone (106); a first reactive interactor (108) arranged towards a first end of the protein backbone (106) and configur...
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WO/2024/041607A1 |
The present disclosure provides a multi-state one-time programmable memory circuit, comprising a memory cell and a programming voltage driving circuit. The memory cell comprises a metal oxide semiconductor field effect storage transistor...
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WO/2023/245762A9 |
A memory chip test method and apparatus (500), and a medium and an electronic device (600). The memory chip test method comprises: sending a mode register write command to a memory chip, and controlling the memory chip to enter a read-wr...
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WO/2024/043967A1 |
A heat‑assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole that has a recess in the NFT-facing ...
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WO/2024/041708A1 |
The invention relates to a method for storing modifiable information in a secure manner against falsification using a continuously expandable data volume of superimposed data sets, wherein a first data set contains the modifiable informa...
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