Title:
CLOCK ARCHITECTURE OF MEMORY, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/045354
Kind Code:
A1
Abstract:
The present disclosure relates to the field of the design of semiconductor circuits. Provided are a clock architecture of a memory, and a memory. The clock architecture of the memory comprises: an on-chip system, which is configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal, and a fourth oscillation signal that have the same frequency and amplitude, wherein the phase difference between the first oscillation signal and the second oscillation signal is 90 degrees, the phase difference between the first oscillation signal and the third oscillation signal is 180 degrees, and the phase difference between the first oscillation signal and the fourth oscillation signal is 270 degrees; and a memory chip, which is configured to output a data signal on the basis of signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal, and the fourth oscillation signal, and to output a command/address signal on the basis of the signal edges of the first oscillation signal and the third oscillation signal, wherein the signal edges are rising edges or falling edges.
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Inventors:
CHENG JINGWEI (CN)
Application Number:
PCT/CN2022/132406
Publication Date:
March 07, 2024
Filing Date:
November 17, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/4076
Foreign References:
| CN114464226A | 2022-05-10 | |||
| US20190180803A1 | 2019-06-13 | |||
| US20070101177A1 | 2007-05-03 | |||
| CN1222791A | 1999-07-14 | |||
| CN103532522A | 2014-01-22 |
Attorney, Agent or Firm:
BOXIN CHINA INTELLECTUAL PROPERTY (CN)
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