Title:
MEMORY DEVICE AND CONTROL METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/082455
Kind Code:
A1
Abstract:
Embodiments of the present disclosure provide a memory device, comprising: a cyclic redundancy check (CRC) circuit (200) configured to indicate whether a CRC error has been detected from data transmission of a host device and the memory device, the CRC circuit (200) comprising: a detection module (210) configured to generate a CRC signal to correspondingly indicate that N CRC errors have been detected from the data transmission of the host device and the memory device, wherein the CRC signal comprises N pulses corresponding to the N CRC errors, and N is an integer greater than 1; and a warning signal generation module (230) configured to generate a warning signal when a time interval between any two adjacent pulses in the CRC signal is less than or equal to a first preset time interval, wherein the warning signal comprises two pulses corresponding to the two adjacent pulses in the CRC signal.
Inventors:
HUANG ZEQUN (CN)
Application Number:
PCT/CN2023/070381
Publication Date:
April 25, 2024
Filing Date:
January 04, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G06F11/32; G06F11/10; G06F11/30; G11C29/44
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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