Title:
DELAY PHASE-LOCKED LOOP AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/082527
Kind Code:
A1
Abstract:
Provided in the embodiments of the present disclosure are a delay phase-locked loop and a memory. When starting to operate, the delay phase-locked loop determines a phase difference between a reference clock signal and a feedback clock signal, and if the phase difference is relatively large, the delay phase-locked loop converts the phase difference into an initial value of a coarse-tuning control code; and if the phase difference is relatively small, the delay phase-locked loop does not perform conversion.
Inventors:
ZHANG XUEYAN (CN)
JUNG JAEHUN (CN)
JUNG JAEHUN (CN)
Application Number:
PCT/CN2023/081158
Publication Date:
April 25, 2024
Filing Date:
March 13, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/4076; H03L7/081
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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