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WO/2024/092838A1 |
A data transmission method and apparatus. The method comprises: a first device generates a first random bit sequence, and determines a total key entropy amount according to the length of the first random bit sequence; the first device de...
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WO/2024/091708A1 |
Methods, apparatus, and computer readable storage medium for performing interleaved scalar multiplication are described. The method includes obtaining a bit-number of a scalar; factorizing the bit-number of the scalar into a product of a...
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WO/2024/091234A1 |
In some embodiments, a system includes a processor and a non-transitory computer readable medium coupled to the processor. In some embodiments, the non-transitory computer readable medium includes code that performs a first character ass...
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WO/2024/090770A1 |
The present invention relates to a low-power quarter round operator, which is provided to reduce power consumption of a quarter round operator by processing a quarter round operation used in stream ciphers at high speed by using hardware...
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WO/2024/090659A1 |
The present invention relates to a method for verifying a signature during transmission and reception of a message between computing devices. The signature verification method performed in a computing device, according to the present inv...
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WO/2024/073771A3 |
An example device includes a user interface component that implements a user interface and receives a visualization request value from user operations; an inspection database comprising an aggregation of inspection data; and a controller...
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WO/2024/082377A1 |
Disclosed in the present invention is a D6T in-memory computing accelerator capable of always linearly discharging and reducing numeric steps. In the in-memory computing accelerator disclosed in the present invention, three effective tec...
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WO/2024/082674A1 |
The embodiments of the present application relate to the technical field of chips. Provided are a floating-point data precision conversion method and apparatus, which improve the invariance of the overall mean value when high-precision d...
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WO/2024/085960A1 |
Embodiments of the present disclosure include systems and methods for transposing matrices based on a multi-level crossbar. A system may include a memory configured to store a matrix comprising a plurality of elements arranged in a set o...
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WO/2024/086261A1 |
Systems and methods are provided for comparing a first number Abit with a second number Bbit. A method includes receiving, from a first computing device associated with the first number Abit, a share a1 bit and a share b1 bit; receiving,...
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WO/2024/079117A1 |
This disclosure relates to apparatus and methods for generating a random number. It is desirable for random numbers to have minimal or no bias towards any of their possible values, such that each possible value that the random number cou...
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WO/2024/076165A1 |
Disclosed is a method for generating an NPU command, comprising the steps of: generating a p-th partial network having the same structure as a structure of a first network defined by a first group of layers included in a predefined neura...
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WO/2024/076163A1 |
Disclosed is a neural network computation method comprising the steps of: reading a partial input activation [1][p] from an external memory connected through a bus and storing the partial input activation [1][p] in a first bank of an int...
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WO/2024/074170A1 |
The quantum process-based generator (28) for real random numbers (411, 418) has an entropy source (401), and the quantum process-based generator (28) for real random numbers (411, 418) evaluates a signal (405) of the entropy source (401)...
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WO/2024/077245A2 |
Disclosed are methods for implementing a hybrid computing environment. In some embodiments, the hybrid environment may include both a coding environment and a spreadsheet application. In some embodiments, the hybrid environment supports ...
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WO/2024/065217A1 |
Methods and apparatuses of the disclosure can dynamicly generate randomness for a given blockchain based on data in blocks of other blockchains. It is able to dynamicly generate randomness that cannot be predicted in advance or biasable ...
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WO/2024/068589A1 |
Computer-implemented method for obtaining information associated with a characteristic of entropy generated by a physical entropy generator, the method comprising: obtaining, from a distribution function of a signal output by the physica...
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WO/2024/066091A1 |
The present application relates to the technical field of data processing, and discloses a data processing method and apparatus, a non-volatile readable storage medium, and an electronic device. The method comprises: acquiring compiling ...
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WO/2024/071465A1 |
The present invention relates to a low-specification electronic control unit (ECU) wireless update security system for a vehicle, comprising a security processing module which is linked to an ECU of a vehicle so as to verify firmware for...
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WO/2024/069332A1 |
The present invention discloses a computer implemented method (50) and a system (100) for converting chance based board games into a skill based game. The method comprising: registering players, initiating the board game, providing a num...
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WO/2024/072937A1 |
A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y ...
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WO/2024/066545A1 |
Embodiments of the present disclosure provide a cache management method and device for multi-port reading and writing. The method comprises: dividing a multi-port RAM cache on a chip into an array of M×N cache units, wherein the multi-p...
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WO/2024/072251A1 |
Embodiments of the present application provide a system for matrix multiplication. According to the proposed system, a residue number system (RNS) is configured to enable a multi-size support in matrix multiplication hardware acceleratio...
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WO/2024/073661A1 |
A wireless transmit/receive unit (WTRU) may receive a configuration. The configuration may include at least one of an artificial intelligence machine learning (AI/ML) operation type association to a traffic category. The traffic category...
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WO/2024/072529A1 |
Generally discussed herein are devices, systems, and methods for digital signature generation security. A method can include generating, by a first device, a first random number, in generating a signature for a communication, masking, us...
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WO/2024/072852A1 |
Methods and systems for wave-based computation are provided. In one aspect, a wave-based computer includes an input circuit configured to receive a dividend and generate a plurality of prime waves and a dividend wave based on the receive...
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WO/2024/064538A1 |
An integrated circuit that combines transpose and compute operations may include a transpose circuit coupled to a set of compute channels. Each compute channel may include multiple arithmetic logic unit (ALU) circuits coupled in series. ...
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WO/2024/062211A1 |
Methods, apparatus, and systems are provided for calculating a lower bound for a conditional minimum entropy per data value associated with a source for a pre-determined confidence value ϵ, such that the probability of the conditional m...
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WO/2024/063959A1 |
A routing circuit for an integrated circuit configured to access a set of resources that are organized according to a topology with a plurality of dimensions. The routing receives a request for a particular resource of the set of resourc...
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WO/2024/063874A1 |
Techniques are disclosed relating to instruction set architecture support for matrix manipulations. In disclosed embodiments, front-end circuitry is configured to fetch and decode a matrix multiply instruction for execution, including to...
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WO/2024/064131A1 |
A method including receiving injector-producer pair parameters for injectors and producers in a target underground region. The injectors and the producers may be characterized as injector-producer pairs. The method also includes converti...
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WO/2024/062071A1 |
The present invention relates to a method for securing against side channel attacks an execution of a cryptographic process comprising a modular exponentiation operation using a secret key d comprising: computing (S3) a result of said op...
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WO/2024/063844A1 |
Techniques are disclosed relating to dedicated power function circuitry for a floating-point power instruction. In some embodiments, execution circuitry is configured to execute a floating- point power instruction to evaluate the power f...
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WO/2024/064085A1 |
Embodiments relate to devices, circuits, and systems including s-bit generators constructed from memtransistors. Each memtransistor is stacked on a non-volatile and programmable local back-gate stack. Each memtransistor has a 2D channel ...
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WO/2024/058208A1 |
A quantum gate device 1 comprises: a quantum bit substrate unit 10 on which at least two data quantum bits, namely, a first data quantum bit 11 and a second data quantum bit 12, and a coupler quantum bit 13 disposed between the first dat...
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WO/2024/055872A1 |
This application describes hybrid hardware accelerators, systems, and apparatus for performing various computations in neural network applications using the same set of hardware resources. An example accelerator may include weight select...
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WO/2024/058572A1 |
A multi-bit accumulator includes 1-bit Wallace trees each configured to perform an add operation on single-bit input data, tristate logic circuits each configured to output a result of the add operation of the 1-bit Wallace trees accordi...
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WO/2024/054800A1 |
Aggregation and scoring system for collecting and analyzing public and survey data of public entities, private entities, elected officials, candidates for public office, and other individuals or entities who hold a position of public or ...
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WO/2024/052207A1 |
The present invention relates to an electronic system for determining, during use of the electronic system, a most frequent value in a data array, A, comprising a plurality of N data values A[i], i=1,…,N, N≥4, each data value A[i] co...
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WO/2024/045824A1 |
Disclosed in the present application is a carry logic circuit. First to fifth input ends of a first lookup table of the carry logic circuit are respectively used for receiving first to fifth input signals, a first output end of the first...
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WO/2024/045301A1 |
Disclosed in the present invention are a full adder circuit and a multi-bit full adder. In the full adder circuit, in-memory computing field-effect transistors store data and perform logic operation on the data in the transistors and loa...
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WO/2024/045665A1 |
The present disclosure relates to the field of data processing. Provided are a multiple-point multiplication operation system, a graphics processor, an electronic apparatus, an electronic device and a multiple-point multiplication operat...
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WO/2024/045825A1 |
The present application relates to the technical field of integrated circuits, and discloses a lookup table circuit. A first input terminal to fifth input terminal of a first lookup table are respectively configured to receive a first in...
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WO/2024/042117A1 |
Method for Performing an Operation in a Cryptographic Application The present invention relates to a method for deriving one or more parameters determining a representation of a variable used when performing an operation on an input oper...
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WO/2024/042403A1 |
A method for correcting spatially variable electron flux in a true random number generator (TRNG) is presented. The TRNG comprises a radioactive source and an array of detectors, and the method comprises: (a) segmenting the array of dete...
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WO/2024/042113A1 |
The present invention relates to a method for designing a device for performing a multiplication of polynomials in a cryptographic application. The method comprises : - dividing the performance of the multiplication of polynomials over a...
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WO/2024/039443A1 |
Techniques are disclosed relating to polynomial approximation of the base-2 logarithm. In some embodiments, floating-point circuitry is configured to perform an approximation of a base-2 logarithm operation and provide a fixed unit of le...
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WO/2024/039447A1 |
Feature discovery includes determining what a user is doing or trying to do with respect to a computer platform from situational awareness information relating to the user's use of the platform. Feature discovery logic is applied to the ...
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WO/2024/033168A1 |
A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a G...
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WO/2024/035388A1 |
A circuit comprises: a random number generator configured to generate a random number; hashing circuitry configured to mimic a hashing function that can transform the random number into a hash value; and retrieving circuitry configured t...
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