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WO/2023/003756A2 |
Aspects of the present disclosure involve a cryptographic processor that includes a systolic array having a plurality of processing lanes (PLs), each PL including a systolic subarray of two or more processing elements (PEs), each PE bein...
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WO/2023/001936A1 |
A true random number generator (TRNG) is disclosed that includes an enclosure. The enclosure encloses radioactive source defining a radioactive source surface and a cavity separating the radioactive source from an array of cells that def...
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WO/2023/003923A1 |
A method may create RTL for a circuit design utilizing DSP blocks by receiving a software program comprising a multiplication statement to multiply a first number by a second number, the first number having a first data type and a first ...
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WO/2023/000110A1 |
An apparatus and a method for accelerated processing of an arithmetic operation. The apparatus comprises an operand pre-arithmetic status register configured to generate a status notification that flags that one of predetermined combinat...
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WO/2023/001938A1 |
In a first embodiment, a true random number generator is presented that includes a CMOS matrix detector with a top surface. A shell is positioned over the top surface and the shell includes a radiation source and a luminophore or scintil...
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WO/2023/003737A2 |
Aspects of the present disclosure involve a cryptographic processor that includes four or more multiplication circuits, two or more addition circuits, and two or more memory circuits. The cryptographic engine is configured to perform a v...
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WO/2023/000304A1 |
Embodiments of the present application provide a method for an entropy service and related products. In the method, a first communication channel is established between a first device and a second device, the second device then transmits...
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WO/2023/003639A1 |
Apparatus and methods are disclosed for performing matrix operations, including operations suited to neural network and other machine learning accelerators and applications, using dual exponent formats. Disclosed matrix formats include s...
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WO/2023/287589A1 |
The subject matter described herein provides systems and techniques for the design and use of multiply-and- accumulate (MAC) units to perform matrix multiplication by systolic arrays, such as those used in accelerators for deep neural ne...
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WO/2023/288205A1 |
Devices can be configured to broadcast blocks incorporating artifact origination tokens. Devices can include network interfaces, memory; and processors. Processors can be configured to obtain artifact-to-time association elements. Artifa...
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WO/2023/283661A1 |
A computer-implemented method for generating at least one random number (10), comprising: • determining at least one measured seed value (6) with at least one sensor (1) • based on the at least one measured seed value (6), determinin...
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WO/2022/248714A9 |
A computer-implemented method for the encoding of, and computation on, distributions of data, the method comprising: obtaining a first set of data items; obtaining a second set of data items; generating a first tuple containing parameter...
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WO/2023/278016A1 |
Two commands each perform a partial complex multiply and accumulate. By using these two commands together, a full complex multiply and accumulate operation is performed. As compared to traditional implementations, this reduces the number...
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WO/2023/278475A1 |
Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reduced input can inclu...
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WO/2023/278126A1 |
A processing device is provided which comprises a plurality of compute units configured to process data, a plurality of arithmetic logic units, instantiated separate from the plurality of compute units, and configured to store the data a...
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WO/2023/275504A1 |
An apparatus comprises a divide/square-root pipeline comprising: a plurality of divide/square-root iteration pipeline stages each to perform a respective iteration of a digit- recurrence divide or square root operation; and signal paths ...
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WO/2023/274872A1 |
The present invention relates to a method for generating a random value (100) by means of a microcontroller (104), wherein an analog temperature signal (110) of an internal temperature sensor (106) of the microcontroller (104) is digital...
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WO/2022/267038A1 |
An embodiment of the present disclosure provides a random sequence generation method and apparatus, a device, and a medium. The method is used for generating a random sequence by using multiple state machines, any of the multiple state m...
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WO/2022/271244A1 |
The present disclosure describes a digital signal processing (DSP) block (26) that includes a columns (102) of weight registers (104) that can receive values and inputs that can receive multiple first values and multiple second values, w...
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WO/2022/269369A1 |
Disclosed herein is system 102 and method for examining relevancy of documents. The system 102, based on request from the user extracts documents from one or more data sources 210. The system 102 then obtains from the user, user intentio...
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WO/2022/271608A1 |
A floating point multiplier-accumulator (MAC) multiplies and accumulates N pairs of floating point values using N MAC processors operating simultaneously, each pair of values comprising an input value and a coefficient value to be multip...
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WO/2022/269731A1 |
A random number generation device (1) is provided with: a photon generation unit (10) which generates and outputs photons; a first polarization unit (20) which converts input photons into polarized light in a first polarization direction...
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WO/2022/271163A1 |
A computer processing system have includes a processing unit operably configured to perform a plurality of exponentiation operations and a cryptosystem controller operably configured to load an exponent from the at least one exponentiati...
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WO/2022/268364A1 |
The invention relates to a method for changing a masking from a Boolean mask to an arithmetic mask with a modulus (2m *p), wherein m is a whole number which is greater than or equal to null, and p has at least one prime divisor which is ...
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WO/2022/264238A1 |
A cumulative calculation device according to an embodiment calculates the accumulation of n values v1, ..., vn for an associative binary operation, and comprises: a selection unit which selects integers i0, ..., im that satisfy i0=1, im=...
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WO/2022/263280A1 |
A tensor of a first select dimension is reformatted to provide one or more sub-tensors of a second select dimension. The reformatting includes determining a number of sub-tensors to be used to represent the tensor. The reformatting furth...
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WO/2022/266676A2 |
Various embodiments provide for a circuit package including an electronic integrated circuit comprising a plurality of processing elements, and a plurality of bidirectional photonic channels, e.g., implemented in a photonic integrated ci...
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WO/2022/259009A1 |
In the present invention, the divider circuit divides two integer numbers using a novel hardware and circuit implementation technique to get the resultant quotient and the residue or remainder, based on using Modified Divisor (MDr) and v...
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WO/2022/260670A1 |
A computing system performs the method of extracting entity features from a relational database. The method includes: extracting the table structures from the relational database; converting the table structures to neural network structu...
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WO/2022/260672A1 |
A low footprint resource sharing hardware architecture that is implemented as a co-processor and is operably configured to perform a plurality of cryptographic algorithms for Dilithium-DSA at all NISTrecommended post-quantum cryptography...
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WO/2022/261198A1 |
In some aspects described herein, a computer-based system that is capable of constructing digital documents is provided. In some implementations, a machine learning system is provided that learns certain terms within a document. The term...
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WO/2022/254011A1 |
Some embodiments are directed to a computer-implemented method to convert a first computation network of operations into a second computation network of operations. The operations of the second computation network being fully homomorphic...
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WO/2022/254010A1 |
Some embodiments are directed to a computer-implemented method for converting a first computation network of operations arranged to compute a function into a second computation network of FHE operations arranged to compute the same funct...
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WO/2022/253287A1 |
Disclosed are an apparatus for generating a random number, an integrated circuit chip, a board, an electronic device, and a method for generating a random number. The apparatus can be comprised in a combined processing apparatus, and the...
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WO/2022/255561A1 |
Disclosed is a pooling method for pooling input data, which may be expressed as a matrix, by means of a pooling window having a size represented by the respective row-directional and column-directional sizes Rp and Cp, the pooling method...
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WO/2022/256293A1 |
An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs...
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WO/2022/248117A1 |
This method is implemented within a digital processor by: a) interrogating an internal register (R1... R(n)) of the processor, the content (b(n)... b0) of which is modified over time; b) extracting n bits from the register at a given tim...
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WO/2022/251341A1 |
Embodiments of the present disclosure are directed to methods for multi-party fixed point multiplication. The methods can include replicated methods for multi-party fixed point multiplication where the inputs and output are represented u...
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WO/2022/249008A1 |
A logic circuit for anti-circular shift-and-add multiplication of an input vector and a binary vector. The logic circuit includes a plurality of input array pairs, a plurality of shift-and-add modules, and an output datapath. A shift-and...
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WO/2022/247194A1 |
The present disclosure provides a multiplier, a data processing method, a chip, a computer device and a storage medium. The multiplier comprises a control circuit and a multiplication operation circuit, wherein the control circuit is use...
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WO/2022/249963A1 |
Provided is a reduced quantum circuit that yields, on an NISQ device, a similar computation result to a quantum algorithm which requires quantum gate operations multiple times. This quantum circuit obtains a final state by performing ope...
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WO/2022/248963A1 |
Provided is a new semiconductor device. In reservoir computing using an input layer, a reservoir layer, and an output layer, the present invention uses variation among threshold voltages of transistors as a weight for use in a product ar...
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WO/2022/251883A1 |
The present disclosure relates to techniques for determining insights from disparate data sets provided from multiple different data sources in a manner that complies with applicable privacy and data protection regulations. More particul...
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WO/2022/246639A1 |
Apparatuses, systems, and techniques for scheduling deep learning tasks in hardware are described. One accelerator circuit includes multiple fixed-function circuits that each processes a different layer type of a neural network. A schedu...
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WO/2022/243781A1 |
In an approach, a process stores a matrix of multibit values for a computation in an analog multiply-accumulate unit including at least one crossbar array of binary analog memory cells connected between respective pairs of word- and bit-...
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WO/2022/245696A1 |
A centralized document system receives a request to merge a first document package associated with a first party and a second document package associated with a second party. The first document package includes a first set of documents a...
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WO/2022/244022A1 |
Disclosed is a method and system for predicting time points for pharmacokinetic studies of a drug under test (DUT). The method comprises receiving drug data, and training data, as input, identifying a plurality of input variables from a ...
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WO/2022/243689A1 |
There is provided a computer implemented method of performing an operation, the method comprising: for a first value corresponding to a first point on a first elliptic curve of a first type defined on a finite field, obtaining a second v...
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WO/2022/239967A1 |
An electronic device and a control method thereof are disclosed. The electronic device according to the present disclosure comprises: a memory which stores a scaling factor of a neural network model; and a processor which obtains quantiz...
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WO/2022/238045A1 |
The invention relates to a computer-implemented method (100) for estimating a metric quantity based on a first and second data series, said method (100) comprising: at least one iteration of a phase of estimating (102) the metric quantit...
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