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WO/2023/158426A1 |
The method includes obtaining, by at least one processor of at least one first network node within a communication network, at least one first key performance metrics (KPM) data type, from a plurality of KPM data types, the plurality of ...
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WO/2023/158193A1 |
The present disclosure suggests an electronic device for generating a homomorphic encrypted text and a method thereof, the electronic device including at least one processor, wherein the at least one processor may: identify n messages; e...
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WO/2023/150231A1 |
A system and method of quickly and efficiently generating a series of random numbers from a source of random numbers in a computing system. Steps includes: loading a data loop (a looped array of stored values with an index) with random d...
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WO/2023/147785A1 |
The present invention belongs to the technical field of Internet-of-Vehicles security. Disclosed are an Internet-of-Vehicles communication security authentication method, system and device based on a national cryptographic algorithm. The...
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WO/2023/149935A1 |
Embodiments of the present disclosure include a multiply-accumulator (MAC) array circuit comprising an activation cache and a plurality of multiply-accumulator (MA) groups. The activation cache comprises cache lines configured to store s...
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WO/2023/150014A1 |
Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may configure a BVH structure including a plurality of nodes, the BVH structure being associated wit...
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WO/2023/147718A1 |
The present disclosure relates to the technical field of computers, and particularly to the field of deep learning and the field of distributed computing. Provided in the present disclosure are a content initialization method and apparat...
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WO/2023/149662A1 |
Disclosed in one embodiment is a data processing method comprising the steps of: acquiring at least one weight, corresponding to at least one input value with respect to at least one from among a plurality of output channels correspondin...
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WO/2023/150027A1 |
Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a BVH structure including a plurality of nodes each including one or more primitives, and eac...
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WO/2023/147770A1 |
A floating point number operation method, applied to multiplication operation of a first floating point number and a second floating point number. The first floating point number comprises a first symbol, a first exponent, and a first ma...
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WO/2023/148411A1 |
Disclosed is a method for calibrating graphs, by means of artificial intelligence, which coordinates the abscissas and ordinates of two or more graphs to compare them. The method comprises: recognising the units of the abscissa and ordin...
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WO/2023/148580A1 |
Provided is a method for operating a semiconductor device that performs data writing and correction processing. The present invention is a method for operating a semiconductor device that includes a control circuit, a first circuit, a se...
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WO/2023/141936A1 |
Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as Montgomery multiplication with reduced interdependencies, using optimized processing resources.
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WO/2023/144039A1 |
A computer-implemented method for enabling elliptic curve arithmetic to be performed using blockchain transactions. A first script of a first blockchain transaction is generated, comprising a modular inversion script configured to obtain...
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WO/2023/146563A1 |
A method includes causing an evaluation profile user interface to be output by a display. The evaluation profile user interface includes a key performance indicator (KPI) input field to receive a user input identifying one or more select...
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WO/2023/147025A1 |
Methods, systems, and computer program products are provided for energy efficient generation of artificial noise to prevent side-channel attacks. An example method includes storing at least one secret value including secret value bits. A...
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WO/2023/144577A1 |
A hybrid time-shared iterative multiply-accumulate circuit comprises a product storage circuit, a multiply circuit operable to receive a first input value, receive a second input value, produce a product of the first input value and the ...
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WO/2023/141933A1 |
Disclosed are apparatuses, systems, and techniques to perform and facilitate fast and efficient modular computational operations, such as modular division and modular inversion, using shared platforms, including hardware accelerator engi...
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WO/2023/137696A1 |
Disclosed in the present application are a logical operation storage unit, a storage array and a logical operation memory. The logical operation storage unit comprises a logical operation control circuit, a result storage circuit, a WBL ...
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WO/2023/134130A1 |
Disclosed in the present application are a Galois field multiplier and an erasure coding and decoding system. The Galois field multiplier comprises a plurality of basic operation units connected in series and a plurality of cyclic proces...
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WO/2023/134507A1 |
A stochastic calculation method, a circuit, a chip and a device, belonging to the technical field of circuits. A stochastic calculation circuit comprises: a control circuit, which is used to input a control parameter into a pulse input c...
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WO/2023/134905A1 |
Techniques for determining an inner product between a non-binarized first array and a second array using a binary logic unit (201) are provided. The first array is decomposed into a plurality of binarized arrays by determining a respecti...
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WO/2023/131432A1 |
The invention relates to a device for identifying at least one synchronicity range (SB) of two time series of random numbers, a first time series ((Ak)) and a second time series ((Bk)). The device comprises - a first non-deterministic ra...
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WO/2023/133438A1 |
A method for calculating a square root B having N bits of a number X having 2N bits includes iterating on bits bi of square root B starting from the most significant bit until the least significant bit of square root B. For each iteratio...
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WO/2023/124235A1 |
A multi-input floating point number processing method executed by a computer device, the method comprising: obtaining a plurality of floating point numbers to be processed corresponding to a target task, and respectively extracting an ex...
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WO/2023/124561A1 |
A circuit, a multiplier and a circuit optimization method, related to the field of electronic devices and used for realizing the balance between the power consumption and the precision of the multiplier. The circuit comprises a digital a...
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WO/2023/125815A1 |
Embodiments of the present application provide a data processing method and apparatus and an edge computing device. The method comprises: quantizing first input data of a neural network to obtain second input data; determining first outp...
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WO/2023/129347A1 |
Techniques for training a neural network having a plurality of computational layers with associated weights and activations for computational layers in fixed-point formats include determining an optimal fractional length for weights and ...
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WO/2023/129261A1 |
The present disclosure relates to a carry chain logic system that leverages carry in and carry out signals from logic blocks to implement logic functions on programmable hardware (e.g., FPGA hardware). In particular, implementations of t...
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WO/2023/129231A1 |
Embodiments of the present disclosure include a multipurpose multiply-accumulator (MAC) array circuit comprising one or more input memories for receiving operands and a plurality of multiply-accumulator circuits each selectively coupled ...
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WO/2023/129491A1 |
Techniques for task processing based on compute element processing using control word templates are disclosed. One or more control word templates are generated for use in a two-dimensional array of compute elements. Each compute element ...
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WO/2023/124372A1 |
The present disclosure provides a floating-point number processing apparatus and method, an electronic device, a storage medium, and a chip. The floating-point number processing method comprises: acquiring a plurality of floating-point n...
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WO/2023/123617A1 |
A method for quickly calculating a three-dimensional polarization dimension, comprising: determining that an incident light field is a coherency matrix of a partially coherent schell-model beam, and decomposing the coherency matrix into ...
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WO/2023/129469A1 |
Methods, systems, and apparatuses to encode data for storage in genetic materials. For example, a computing system may segment user data into a plurality of data blocks and generate seed data characterizing a plurality of fountain code s...
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WO/2023/124371A1 |
Provided in the present disclosure are a data processing apparatus and method, and a chip, a computer device and a storage medium. The data processing apparatus comprises: a data conversion circuit, which is used for receiving data to be...
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WO/2023/129546A1 |
The technology disclosed provides a system that comprises a processor with computing units on an integrated circuit substrate. The processor is configured to map a program across multiple hardware stages with each hardware stage executin...
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WO/2023/121729A1 |
A field programmable gate array, FPGA, including a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a data masking circuit co...
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WO/2023/118965A1 |
This disclosure is directed to generating a set of data elements for more secure encryption or more resilient decryption associated with generating a target set of conditional data elements. The target set of conditional data elements ma...
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WO/2023/117081A1 |
The invention is notably directed to a method of in-memory processing, the aim of which is to perform matrix-vector calculations. The method relies on a device having a crossbar array structure (15). The latter includes N input lines (15...
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WO/2023/120403A1 |
Provided is a unit that is for calculation by CGRA, that effectively uses a memory space, and that makes it possible to obtain a sparse matrix product by using less local memory. The calculation unit comprises a 3-input pipeline floating...
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WO/2023/121666A1 |
A divide circuit, according to certain embodiments disclosed herein, includes a prescaler and an iterator. The prescaler is configured to prescale a dividend by a prescaling factor to generate a prescaled dividend and to prescale a divis...
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WO/2023/108281A1 |
Cryptographic processor chips, systems and associated methods are disclosed. In one embodiment, a cryptographic processor is disclosed. The cryptographic processor includes a first cryptographic processing module to perform a first logic...
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WO/2023/113906A1 |
Methods, systems and computer program products are provided for improving performance (e.g., reducing power consumption) of a hardware accelerator (e.g., neural processor) comprising hybrid or analog multiply and accumulate (MAC) process...
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WO/2023/111625A1 |
The present disclosure relates to a multimodal system 100 for activity-based carbon footprint prediction contains a plurality of hospitals 102, a data repository unit 104, an information processing unit 106, an analyzing unit 108, a reco...
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WO/2023/109749A1 |
Examples pertaining to optimization of delivery of extended reality (XR) traffic over a wireless link in mobile communications are described. An application implemented in a user equipment (UE) communicates with a network to transmit and...
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WO/2023/111748A1 |
Methods, systems, and computer program products for automated few-shot learning techniques for artificial intelligence-based query answering systems are provided herein. A computer-implemented method includes obtaining multiple sets of q...
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WO/2023/114235A2 |
Multiply-accumulate processors within a tensor processing unit simultaneously execute, in each of a sequence of multiply-accumulate cycles, respective multiply operations using a shared input data operand and respective weighting operand...
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WO/2023/113445A1 |
The present invention relates to a floating point arithmetic technology, and is characterized by: on the basis of the result of comparing exponent parts of at least two operands being input, storing bit information of a mantissa part of ...
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WO/2023/111781A1 |
A computer-implemented method for detecting reference data standardization gaps in data sets is disclosed. The method comprises identifying at least one reference data candidate in a data set, using an index for values of the identified ...
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WO/2023/108422A1 |
An efficient zero knowledge proof accelerator. A hardware carrier having high computing power and high efficiency can be provided for zero knowledge proof calculation; and a fine-grained pipeline architecture is applied to a multi-scalar...
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