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WO/2024/042113A1 |
The present invention relates to a method for designing a device for performing a multiplication of polynomials in a cryptographic application. The method comprises : - dividing the performance of the multiplication of polynomials over a...
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WO/2024/039443A1 |
Techniques are disclosed relating to polynomial approximation of the base-2 logarithm. In some embodiments, floating-point circuitry is configured to perform an approximation of a base-2 logarithm operation and provide a fixed unit of le...
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WO/2024/039447A1 |
Feature discovery includes determining what a user is doing or trying to do with respect to a computer platform from situational awareness information relating to the user's use of the platform. Feature discovery logic is applied to the ...
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WO/2024/033168A1 |
A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a G...
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WO/2024/035388A1 |
A circuit comprises: a random number generator configured to generate a random number; hashing circuitry configured to mimic a hashing function that can transform the random number into a hash value; and retrieving circuitry configured t...
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WO/2024/033771A1 |
Methods, systems, and computer program products may formulate an iterative data mix up problem into a Markov decision process (MDP) with a tailored reward signal to guide a learning process. To solve the MDP, a deep deterministic actor-c...
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WO/2024/035427A1 |
A random number generator comprises a ring generator and one or more inverter-based ring oscillators. The one or more inverter-based ring oscillators is configured to inject bits into the ring generator at a plurality of location. If the...
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WO/2024/027039A1 |
Provided in the present disclosure are a data processing method and apparatus, and a device and a readable storage medium. The method comprises: acquiring an input feature map to be processed and the number of original output channels; w...
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WO/2024/027226A1 |
Disclosed in the present disclosure is a multiplying unit. The multiplying unit comprises a control signal generation module, a multiplexer, one or two 4 * 4 multiplying units and an adder tree, wherein the control signal generation modu...
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WO/2024/025618A1 |
A peripheral device for matrix multiplication including a weight memory, an input memory, a multiplier, an accumulator, an output memory and a sequencer to generate signals to drive the input memory and the output memory and to generate ...
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WO/2024/025674A1 |
A system has a sewer and a processor electrically coupled to the server that receives an input binary string as an input and uses a decision matrix to determine via a plurality of cycles what a next state of a plurality of target cells b...
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WO/2024/025443A1 |
A method of generating a random number is disclosed. The method comprises determining at least three or more random variables based on times of at least four independent events; and using the determined at least three or more random vari...
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WO/2024/016632A1 |
The present invention belongs to the technical field of location. Provided in the embodiments of the present invention are a bright spot location method, a bright spot location apparatus, an electronic device and a storage medium. The me...
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WO/2024/017907A1 |
Computer-implemented method comprising obtaining a bit stream and transforming the bit stream into a floating-point number, wherein the floating-point number comprises an exponent and a significand, the transformation comprising determin...
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WO/2023/126019A9 |
The disclosure provides a data processing method, which can be applied to calculating a histogram of a preset data sequence. Each piece of data in the preset data sequence comprises an exponential part and a mantissa part. The method com...
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WO/2024/013498A1 |
The disclosure provides computer-implemented methods, computing apparatus and computer program products for generating a random number based on genetic information from a biological data source containing at least the genetic information...
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WO/2024/013022A1 |
Computer-implemented method for determining a Gaussian integer congruent to a given Gaussian integer modulo a Gaussian integer modulus, wherein the norm of the Gaussian integer is smaller than the norm of the square of the Gaussian integ...
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WO/2024/008837A1 |
In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A pro...
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WO/2024/007652A1 |
The present invention relates to the field of electromagnetic computation. Disclosed are an accelerated solving method for a large sparse matrix, a system, and a storage medium. For the problems of low efficiency and poor accuracy of exi...
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WO/2023/227064A9 |
A floating-point number compression method, comprising performing the following steps by means of an arithmetic unit: obtaining a plurality of floating-point numbers; generating common multiplying power factors for the floating-point num...
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WO/2024/006900A1 |
A disclosed method for making efficient picks of micro-operations for execution includes selecting a first set of micro-operations that are ready for execution during a certain clock cycle. The method also includes selecting a second set...
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WO/2023/246063A1 |
The present application provides a modular multiplier applied to SM9, comprising: a multiplying circuit used for performing a product operation on two operators in the SM9 to obtain a product of the two operators, wherein the product is ...
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WO/2023/248370A1 |
Provided is a superconducting quantum circuit comprising a coupler which is configured to be able to enhance a four-body interaction by means of a circuit parameter. The superconducting quantum circuit comprises first to a fourth quantum...
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WO/2023/245727A1 |
Embodiments of the present application provide a random data generation circuit and a read-write training circuit. The random data generation circuit comprises: a first shift register and a second shift register, the first shift register...
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WO/2023/244905A1 |
Certain aspects of the present disclosure provide a processor, comprising: a configurable nonlinear activation function circuit configured to: determine, based on a selected nonlinear activation function, a set of parameters for the nonl...
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WO/2023/244602A1 |
Systems, methods, and software products provide increased trust in authentication of a user to an authentication server when a trusted witness client device witnesses the authentication of the user on the user's root client device. Both ...
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WO/2023/239696A1 |
A system and method are provided for generating Unique Digital Signatures (UDS) for semiconductor memories to improve data security. Generally, the method involves allocating a number of native memory cells in a memory device; obtaining ...
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WO/2023/236628A1 |
The present invention belongs to the technical field of information security. Disclosed is a privacy-preserving neural network prediction system. The present invention comprises a client, a server and a third party. In an offline predict...
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WO/2023/234629A1 |
The present invention relates to a quantum random number encryption key generation method, and more specifically to a quantum random number encryption key generation method characterized by comprising: a calling unit for transmitting a r...
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WO/2023/230764A1 |
An optical computing system, which is applied to the field of optical processing. A first optical processing unit in a first optical processing array of the optical computing system is used for outputting a first optical signal according...
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WO/2023/235004A1 |
A single-instruction/multiple-data (SIMD) processor uses a function unit that can perform a single operation on multiple data elements. The function unit operates at a higher speed than the rest of the processor, allowing each data eleme...
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WO/2023/231363A1 |
A method for multiplying and accumulating operands, and a device therefor. A computing apparatus is comprised in an integrated circuit apparatus, and the integrated circuit apparatus comprises a universal interconnection interface and ot...
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WO/2023/229700A1 |
Methods and apparatus to generate and display trends associated with a process control system are disclosed. An example apparatus includes memory, machine readable instructions, and processor circuitry to execute the instructions to gene...
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WO/2023/228469A1 |
This quantum bit array chip comprises a semiconductor layer, an insulating layer disposed on the semiconductor layer, a plurality of first gate electrodes which are disposed on the insulating layer, and which apply a voltage to trap elec...
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WO/2023/230184A1 |
A comprehensive confidential information management and communication system and method to gather, maintain, update, and cross-reference information and instructions pertinent to a person's health, social, and financial well-being during...
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WO/2023/226173A1 |
Disclosed in the present invention is a modular multiplication operation method based on a number-theoretic transform prime. A modular multiplication operation ab mod p is performed on a prime field by means of combining a Karatsuba divi...
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WO/2023/222246A1 |
Methods and systems for generating entropy and eliminating non-random components of a Barkhausen effect signal are disclosed. In one method, a Barkhausen signal (BS) is captured by applying a changing magnetic field to a ferromagnetic ma...
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WO/2023/224723A1 |
A processor-implemented method for fast floating point simulations with learnable parameters includes receiving a single precision input. An integer quantization process is performed on the input. Each element of the input is scaled base...
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WO/2023/224866A1 |
A comparator circuit with a speed control element is disclosed herein. The speed control element may include a variable voltage source and one or more transistors. Using a voltage supplied by the variable voltage source, the one or more ...
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WO/2023/215960A1 |
A system, and associated method, includes a plurality of data processing units, a target CPU, an interconnect unit that is separate from the target CPU and configured to a receive data payload and a prefix that includes a sequentially or...
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WO/2023/220229A1 |
A computer-implemented system, method, and computer program product for managing the storage and handling of biological samples and related information using a blockchain stored on a network of computing nodes.
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WO/2023/220537A1 |
Disclosed herein is a fast adder design based on a novel axiomatization of mathematics, of natural and real numbers, by the author. Addition is a Finite State Machine that, on an average, takes log2 n iterations to calculate a n-bit addi...
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WO/2023/215436A1 |
A method for serializing communications in the computing field includes serializing input data into a serialized stream of symbols, based on one or more encodings, at a serializer, each symbol including a disparity code selected based on...
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WO/2023/215048A1 |
One or more zero counters may be configured to count trailing zeros of significands of operands to produce a trailing zero count from the first operand and the second operand. A round-bit position circuit may be configured to determine a...
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WO/2023/207236A1 |
The present application provides a probability bit unit circuit, a probability bit circuit system and a control method therefor, for use in implementing mutual cascading between probability bit unit circuits, thereby improving the degree...
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WO/2023/208431A1 |
A SPAD-based dithering generator, comprising: an array of SPADs for detecting random events emitted from an event source, and a digital logic circuitry combining outputs from the SPADs and generating a N-bit wide random bit sequence.
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WO/2023/211466A1 |
A system and method for random number generation. The method includes receiving, at a first single-photon avalanche diode (SPAD), a first series of photons, converting, by the first SPAD, the first series of photons into a first series o...
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WO/2023/207441A1 |
Provided in the present disclosure is an SRAM storage and computing integrated chip based on capacitive coupling. The SRAM storage and computing integrated chip comprises an input module, a bitwise multiplication module, a capacitance at...
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WO/2023/206832A1 |
The present application relates to the technical field of data processing, and provides a function implementation method, an approximation interval segmentation method for a function, a device, and a medium. In the present application, s...
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WO/2023/204534A1 |
Disclosed is a method of processing an encrypted message. The method of processing an encrypted message includes: performing calculation on a homomorphic encrypted message on an approximate message including an error, and when a proporti...
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