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WO/2024/069340A1 |
The present invention provides a semiconductor device which comprises a transistor of a very small size. This semiconductor device comprises first and second transistors; the first transistor comprises first to third conductive layers, a...
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WO/2024/070915A1 |
The purpose of one aspect of the present invention is to provide a resin that has liquid repellency and high solubility in alkaline solution, the resin being rendered insoluble in solvents through photocrosslinking at a low exposure leve...
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WO/2024/065862A1 |
The present application relates to a wafer handling device, comprising a cylinder assembly and a cover assembly. The cylinder assembly comprises a cylinder block, and a lifting rod, which is movably connected to the cylinder block in a l...
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WO/2024/069816A1 |
Provided is an electrostatic chuck assembly the service life of which can be lengthened several fold during use in a vacuum chamber. This electrostatic chuck assembly comprises a disc-shaped ceramic plate with built-in electrodes serving...
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WO/2024/072525A1 |
An apparatus can include a support structure and a docking station, wherein the apparatus is configured to move the docking station relative to the support structure. The apparatus can further include a head among a plurality of heads. T...
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WO/2024/072670A1 |
Methods, systems, and media for deposition control in a process chamber are provided. In some embodiments, a method comprises (a) obtaining, at a present time, information indicating a status of one or more components of the process cham...
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WO/2024/070825A1 |
The present invention provides: a film formation method for forming a film selectively; and a substrate treatment apparatus. Provided is a film formation method for forming, in a substrate having a first surface and a second surface, a...
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WO/2024/067275A1 |
Disclosed in the present invention are a packaging method for a chip with a high-density connecting layer, and a packaging structure thereof. The method comprises the steps of: S1, preparing a high-density connecting layer with a plurali...
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WO/2024/066247A1 |
Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate (100) comprising an array region (110) and a peripheral region (120) adjacent to each other; a bit line (101)...
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WO/2024/067997A1 |
In one embodiment, the semiconductor device (1) comprises a semiconductor body (2), a gate electrode (33) and a first electrode (31), wherein - the semiconductor body (2) comprises a first region (21) which is a source region or an emitt...
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WO/2024/072816A1 |
Described herein is a method for selectively oxidizing a substrate. The method includes forming a non-conformal layer on at least one side surface of a trench or a hole of a substrate. After forming the non-conformal layer, the at least ...
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WO/2024/070832A1 |
The present invention provides a composition for finish polishing, the composition enabling efficient proceeding of etching, thereby being capable of improving the polishing rate, while maintaining the surface quality after the polishing...
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WO/2024/073209A1 |
Synthesis of cationic-modified water-soluble polysaccharide is disclosed. The cation is pendent to the polysaccharide backbone. Chemical Mechanical Planarization (CMP) slurries comprise abrasives; activator; oxidizing agent; additive com...
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WO/2024/067703A1 |
The present disclosure relates to a method for manufacturing a trench in a semiconductor substrate, and a semiconductor device. The method comprises: providing a semiconductor substrate; forming a hard mask layer on the semiconductor sub...
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WO/2024/068858A1 |
An enclosure is shown, comprising at least a first substrate and a second substrate, wherein the first substrate is transparent at least in part and/or at least for a wavelength bandwidth, at least one common laser weld zone wherein mate...
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WO/2024/071020A1 |
A substrate processing system according to an embodiment of the present disclosure comprises: a plurality of processing units each having a substrate support unit that supports a substrate and a ring disposed around the substrate; a vacu...
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WO/2024/066279A1 |
Provided in the present application are a wafer defect detection method, device and apparatus, and a computer-readable storage medium. The wafer defect detection method comprises: acquiring structure feature information of the surface of...
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WO/2024/070071A1 |
This stage comprises: a first metal plate having a first groove; a second metal plate positioned under the first metal plate and having a through-opening; a third metal plate positioned under the second metal plate and having a second gr...
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WO/2024/069280A1 |
A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first wid...
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WO/2024/065906A1 |
The embodiments of the present disclosure relate to a semiconductor structure and a preparation method therefor. The semiconductor structure comprises a substrate, and one or more layers of array structures, which are arranged on one sid...
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WO/2024/072923A1 |
A method of processing a substrate is disclosed which includes depositing a layer in a processing chamber on a field region, a sidewall region, and a fill region of a feature of the substrate, wherein a hardness of a portion of the layer...
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WO/2024/071182A1 |
The present invention provides a semiconductor manufacturing treatment liquid that is excellent in flaw removability for specific materials when used for washing a treated object containing at least one (specific material) selected from ...
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WO/2024/067569A1 |
Disclosed in the present application are a chip assembly, an electronic device and a manufacturing method for a chip assembly, relating to the technical field of communication devices. The chip assembly comprises a substrate, a bonding l...
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WO/2024/069281A1 |
A first VTFET is provided on a wafer. A second VTFET is adjacent to the first VTFET on the wafer. A backside power deliver network is on a backside of the wafer. A shared frontside contact is on a frontside of the wafer. The shared front...
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WO/2024/066124A1 |
The present disclosure provides a chip packaging method and a chip packaging structure. The chip packaging method includes: providing an encapsulated grain and a packaging substrate, the encapsulated grain including a first hybrid bondin...
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WO/2024/070624A1 |
[Problem] To provide a storage system capable of broadly ensuring available floor space while densely storing products. [Solution] A storage system 100 which is equipped with: a port 10 in which a first container 11 for storing a semicon...
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WO/2024/070957A1 |
A signal transmission device according to the present invention is provided with: a first chip including a first transformer; a second chip; a plurality of first lead terminals; a plurality of second lead terminals; an inter-chip wire el...
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WO/2024/066783A1 |
Provided in the present disclosure are a manufacturing method for a high-bandwidth die, and a high-bandwidth die. The method comprises: bonding a first metal layer of a first wafer with a first metal layer of a second wafer; thinning a s...
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WO/2024/070696A1 |
This film formation method includes (A) and (B) below. (A) A substrate is prepared, the substrate having, in different regions of the surface thereof, a first film and a second film formed from a different material than the first film. (...
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WO/2024/070151A1 |
The present invention is a susceptor for performing epitaxial growth on a wafer that has a main surface (110), the susceptor for epitaxial growth comprising a pocket for placing the wafer, and a peripheral part that surrounds the pocket,...
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WO/2024/070580A1 |
Provided is a technology for improving the controllability of plasma generated on a substrate. This plasma processing device comprises: a chamber; a substrate supporting part which is disposed within the chamber and which includes a lo...
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WO/2024/070800A1 |
A method for producing a semiconductor device which comprises: forming a lower electrode on a substrate; forming, on the lower electrode, a high-permittivity film comprising an oxide containing a tetravalent metal cation; forming, on the...
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WO/2024/070801A1 |
This substrate treatment method includes: forming an Ru film on a substrate through electroless plating; carrying out a treatment using an inert-gas plasma on the substrate on which the Ru film is formed; and carrying out a reduction tre...
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WO/2024/070239A1 |
Provided is a method for growing a single crystal of a gallium oxide-based semiconductor, the method comprising a step of growing a single crystal under an oxidizing atmosphere from a melt in which a raw material of the single crystal is...
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WO/2024/072646A1 |
The disclosure relates to a substrate support assembly and apparatus for measuring the temperature of a substrate disposed on the support assembly. In one embodiment, a substrate temperature measurement apparatus includes a substrate sup...
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WO/2024/070678A1 |
Provided is a technology capable of precisely bringing a probe into contact with an electrode formed on an object to be inspected. Provided is an inspection method that is executed by an inspection device comprising a placement stage on ...
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WO/2024/070818A1 |
Provided is a method which is for controlling a lifter pin and is for performing substrate delivery between a conveyance arm on which a multistage effector is mounted and a stage inside a processing module of a substrate processing devic...
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WO/2024/070268A1 |
A plasma treatment device according to the present invention comprises: a plasma treatment chamber; a substrate support body that includes a lower electrode, an electrostatic chuck, and an edge ring; an upper electrode that is disposed a...
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WO/2024/070009A1 |
This treatment method is for chips and uses an electrostatic carrier which includes a body part having an electric conductivity and having a plurality of through-holes in the thickness direction, and an insulating layer formed on a surfa...
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WO/2024/071069A1 |
A wiring board according to the present disclosure comprises: an insulating board that has a first surface and a second surface which is positioned on the reverse side from the first surface; and a solder resist that is positioned on the...
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WO/2024/065106A1 |
The present application relates to the technical field of displays. Disclosed are an array substrate and a display panel. A plurality of first patterns are designed on one side of a row drive area of the array substrate, and it is ensure...
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WO/2024/069737A1 |
Provided is an inspection method for inspecting the electrical characteristics of a pattern on a sample where a pattern 102 comprising a conductor or a semiconductor has been formed in a dielectric region 101. A secondary electron image ...
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WO/2024/071631A1 |
The present invention relates to a method for manufacturing a semiconductor device. More specifically, the method for manufacturing a semiconductor device comprises the steps of: (a) providing a substrate; (b) forming an oxide film on th...
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WO/2024/065110A1 |
The present application relates to the technical field of display, and discloses a thin film transistor and a preparation method, and a display panel. Since the concentration of hydrogen in a semiconductor layer of the thin film transist...
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WO/2024/069445A1 |
A power module includes: a fin housing including a fluid passage; a power switch having an exterior surface; and a fin system comprising a plurality of fins attached to a base plate, the plurality of fins extending from the base plate an...
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WO/2024/068453A1 |
Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of ...
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WO/2024/070026A1 |
The present invention concerns a method for manufacturing a package of a power semiconductor and a package comprising a power semiconductor. The package comprises: conducting layers over each electrode of the power semiconductor, nanowir...
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WO/2024/069721A1 |
Provided is an invention with which it is possible to suppress an imbalance in a supply amount of processing gas in the surface of a substrate. The present invention comprises a processing chamber that processes a substrate, a substrat...
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WO/2024/072609A1 |
Embodiments of the disclosure relate to techniques and apparatus for reducing out-of-plane distortion (OPD) in a substrate, as well as control of the effects of OPD and the effects that the modifications made to the substrate to correct ...
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WO/2024/065861A1 |
The present application relates to a furnace tube device. The furnace tube device comprises a reaction container, a collection container and a temperature control assembly. The temperature control assembly comprises a connecting tube, a ...
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