| Document |
Document Title |
|
WO/2020/173656A1 |
An ADC system comprises a coarse ADC for determining a coarse word (CW) representing an input signal, and an incremental ADC (IADC) for determining a fine word (FW) based on a combination of the input signal and a feedback signal. A firs...
|
|
WO/2020/173558A1 |
An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (105l-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a fir...
|
|
WO/2020/175581A1 |
The present invention is provided with: a subtractor 1 that calculates the difference between an input digital signal and a feedback signal; an integrator 2 that integrates this difference; a quantizer 3 that quantizes an integrated valu...
|
|
WO/2020/135958A1 |
A method of processing an analog signal includes receiving, into a signal processing circuity, an analog signal from a sensor, the signal processing circuitry having an offset voltage. The method includes receiving, into the signal proce...
|
|
WO/2020/123363A1 |
Herein disclosed are some examples of metastability detectors and compensator circuitry for successive-approximation-register (SAR) analog-to-digital converters (ADCs) within delta sigma modulator (DSM) loops. A metastability detector ma...
|
|
WO/2020/115065A1 |
The invention relates to a circuit arrangement for an incremental delta-sigma modulator, the circuit arrangement comprising at least one incremental delta-sigma modulator and a sample-and-hold element, wherein the sample-and-hold element...
|
|
WO/2020/112291A1 |
Examples relate to a conversion circuitry, a means for converting, a conversion method, a Delta-Sigma-modulator, a Delta-Sigma-modulation means, a digital to analog conversion circuit, a digital to analog conversion means, a mobile devic...
|
|
WO/2020/109320A1 |
A sigma-delta analog-to-digital converter comprises first and second injection branches (101, 102) and first and second feedback branches (121, 122) connected to an integration node (120). The first and second injection branches are conf...
|
|
WO/2020/110558A1 |
This variation suppressing circuit suppresses variations in a reference voltage supplied to a switched capacitor circuit (2, 42, 52) of a differential configuration. The switched capacitor circuit has a configuration in which an input ca...
|
|
WO/2020/072139A1 |
A continuous time sigma delta modulator for use in a continuous time sigma delta analog to digital converter is described. The modulator comprises a sequence of integration stages and a quantizer arranged to receive an output from the la...
|
|
WO/2020/054830A1 |
The present invention mitigates instability in internal state upon sharp change in input in a current input delta-sigma modulator. A signal current is input to a first integrating node. A differential current between a fixed current and ...
|
|
WO/2020/050927A1 |
A radio frequency system. In some embodiments, the system includes a one- bit receiver, and the one-bit receiver includes a digital pseudo random noise generator, a one-bit digital to analog converter, a power combiner, a one-bit analog ...
|
|
WO/2020/050937A1 |
An active filter and an analog-to-digital converter (ADC) configured to suppress out-of-band peaking. An active filter may include an active device configured to provide a power gain to an input signal, a feedback network configured to c...
|
|
WO/2020/040068A1 |
A sound processing device (100) is provided with: a correction unit (112) that, on the basis of asymmetry of a waveform in one carrier frequency when a predetermined input signal is converted to a pulse width modulation (PWM) signal, cor...
|
|
WO/2020/039506A1 |
A communication apparatus (50) includes a path splitting unit configured to split an existing path into two paths, with one path being formed by appending 1 to the existing path and, the other path being formed by appending -1 to the exi...
|
|
WO/2020/037506A1 |
Embodiments of the present application relate to continuously variable slope delta modulation (CVSD)-based encoding and decoding methods and devices. The method comprises: if a+1 encoded values corresponding to (n-a)th to nth signals in ...
|
|
WO/2020/038559A1 |
The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to- digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be so...
|
|
WO/2020/038565A1 |
The invention relates to an interface between a radio receiver on a RF-side and a baseband receiver on a BB-side whereas the radio receiver comprises means for receiving radio frequency signals and an analog-to-digital converter for conv...
|
|
WO/2020/036754A1 |
A signal acquisition or conditioning amplifier can be configured and controlled to use correlated doubling sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power oper...
|
|
WO/2020/028083A1 |
In one embodiment, the present invention is directed to a contact hearing system comprising: an ear tip including a transmit coil, wherein the transmit coil is connected to an audio processor, including an H Bridge circuit; a first input...
|
|
WO/2020/003745A1 |
This audio device is provided with: a first path in which digital-sigma modulation is applied to a sound source signal or a signal generated on the basis of the sound source signal; a second path in which digital-sigma modulation is not ...
|
|
WO/2019/229678A1 |
Circuitry and techniques are described herein for performing accurate and low power conversion of an analog value into a digital value. According to some aspects, this disclosure describes a successive approximation register (SAR) analog...
|
|
WO/2019/228700A1 |
A sensor arrangement (10) comprises a pressure sensor (12) that is realized as capacitive pressure sensor, a capacitance-to-digital converter (13) coupled to the pressure sensor(12) and implemented as a delta-sigma analog-to- digital con...
|
|
WO/2019/231857A1 |
An example sigma delta modulator (SDM) circuit includes a floor circuit (306), a subtractor (308) having a first input coupled an input of the floor circuit and a second input coupled to an output of the floor circuit, and a multi-stage ...
|
|
WO/2019/217088A1 |
Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-si...
|
|
WO/2019/217087A1 |
Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop fi...
|
|
WO/2019/215095A1 |
A Class-D amplifier for generating a driver signal from a multi-bit input signal comprises a digital pulse-width modulation (PWM), stage (DPWM) that is configured to generate a PWM signal (PWMA, PWMB) from the multi-bit input signal and ...
|
|
WO/2019/211236A1 |
The invention relates to an analog-to-digital converter, ADC, based on single-bit delta-sigma quantization. The ADC comprises an integrator (INT), a threshold detector (TD), a feedback block (FBB), a range control circuit (RCC) and an ou...
|
|
WO/2019/206881A1 |
The amplifier load current cancellation in a current integrator comprises applying an input current (Ιin) to an operational transconductance amplifier provided with an integration capacitor (Cint) for current integration, leading an out...
|
|
WO/2019/185633A1 |
The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC...
|
|
WO/2019/185658A1 |
The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC...
|
|
WO/2019/190621A1 |
Systems and methods according to one or more embodiments are provided for improving noise performance in a delta sigma modulator comprising an adder, quantizer and nth order filter. The adder is operable to receive an input signal and a ...
|
|
WO/2019/187262A1 |
A digital transmitter includes baseband interfaces to generate digital baseband signals with baseband frequencies, digital-upconverting stages to upconvert the baseband frequencies to first radio frequencies having a predetermined freque...
|
|
WO/2019/185625A1 |
The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC...
|
|
WO/2019/182730A1 |
A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node a...
|
|
WO/2019/183267A1 |
In some examples, a sigma-delta analog-to-digital converter (ADC) comprises: a first set of switches (120) configured to receive a first voltage signal; and a second set of switches (110) coupled to the first set of switches (120) at a f...
|
|
WO/2019/169316A1 |
A circuit (500) includes a multiplexer (505) having a first input, a second input, a control input, and an output. The circuit (500) further includes a first register (520A) having an input coupled to the output of the multiplexer (505) ...
|
|
WO/2019/161875A1 |
Method for multilevel modulation, in which method a multilevel converter, which comprises a plurality of controllable switches, is actuated by an output signal (204) of an electronic circuit (200), wherein a reference signal which is app...
|
|
WO/2019/157414A1 |
An analog-to-digital converter (ADC) device (100) includes a delta-sigma modulator (102) having at least one integrator (104) and a quantizer (142) configured to receive an output of the at least one integrator (104). The delta-sigma mod...
|
|
WO/2019/147417A1 |
A delta-sigma modulator (DSM) includes: a first summation circuit coupled to an input signal for subtracting an error feedback signal from the input signal; a tunable signal transfer function coupled to the first summation circuit for se...
|
|
WO/2019/137581A1 |
The problem to be solved by the present invention is that of designing the monitoring of a power electronic assembly to be more effective and versatile. This problem is solved according to the invention in that, by means of a power elect...
|
|
WO/2019/134103A1 |
A digital-to-analog converter (100) for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network (200) having a first configuration ...
|
|
WO/2019/133685A1 |
Reference scaling, op amp balancing and chopper stabilization techniques for delta-sigma modulators of analog-to-digital converters are provided. For reference scaling, unit elements in a feedback digital-to-analog (DAC) converter are dr...
|
|
WO/2019/111703A1 |
The present technology relates to a signal processing device, a signal processing method and a program which can improve the modulation rate of a Pulse Width Modulation (PWM) signal. PWM modulation is performed in which: either one of 0 ...
|
|
WO/2019/111446A1 |
This ΔΣ modulator is provided with: a first adder that adds a first input signal and a second input signal having frequencies adjacent to each other; a loop filter; a second adder that adds an output of the first adder and an output of...
|
|
WO/2019/108301A1 |
A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software...
|
|
WO/2019/087809A1 |
According to the present invention, the power consumption of an A/D converter including an adder, a quantizer, a prediction filter, and a decimation filter is reduced. An A/D converter 1A is provided with an adder 2, a quantizer 3, a pre...
|
|
WO/2019/083267A2 |
A semiconductor apparatus according to the present technology comprises: a signal input unit for selecting and outputting multiple input signals according to a channel selection signal; an amplifier for amplifying and outputting an outpu...
|
|
WO/2019/081422A1 |
A sensor arrangement comprises a sensor (1) having a first terminal (3) and a second terminal (5), and an amplifier (9) having an amplifier input (11) for applying an input signal and an amplifier output (13) for providing an amplified i...
|
|
WO/2019/081646A1 |
A residue generation apparatus for use in continuous-time and hybrid ADCs is proposed. The apparatus includes a quantizer for digitizing an analog input to generate a digital output, and means for applying a first transfer function to th...
|
