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WO/2018/026461A1 |
An integrated circuit includes a control circuit, a first-in first-out circuit, and a serializer circuit. The control circuit generates parallel pulse-width modulation data in first parallel pulse-width modulation signals. The first-in f...
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WO/2018/024316A1 |
A device, system and method for improvement of analog/digital conversion. An improved delta sigma - converter including a phase or frequency modulation and demodulation, is used. The improved delta sigma - converter obtains higher gains ...
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WO/2018/010572A1 |
An apparatus, system, and method are provided for affording digital to analog converter (DAC) quantization noise that is independent of an input signal. In operation, an input signal for a DAC is received. Further, a particular signal is...
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WO/2018/009054A1 |
The present invention is related to an auxiliary device that is configured for exchanging data with a main device, preferably a mobile device such as a telephone, laptop, or tablet computer, using the audio jack of the main device. The p...
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WO/2018/009306A1 |
A microphone assembly includes a transducer element and a processing circuit. The processing circuit includes an analog-to-digital converter (ADC) configured to receive, sample and quantize a microphone signal generated by the transducer...
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WO/2018/004617A1 |
In accordance with embodiments of the present disclosure, a method of neutralizing voltage kickback associated with a reference buffer of a switched capacitor based data converter having a first switched capacitor coupled to an output no...
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WO/2018/004826A1 |
A processing system, and associated input device and method are disclosed suitable for reducing a receiver size within the input device. The processing system comprises a delta-sigma modulator comprising one or more input nodes configure...
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WO/2017/220720A1 |
A Sigma-Delta (ΣΔ) modulator for converting an analog input signal having a frequency bandwidth around a variable center frequency f 0 to a digital output signal at a sampling frequency f s . The ΣΔ modulator comprises a quantizer (4...
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WO/2017/211615A1 |
Examples relate to a concept generating at least one RF signal based on at least one digital baseband signal at a first clock rate. At least one digital pulse sequence at a second clock rate corresponding to a center frequency of the RF ...
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WO/2017/208635A1 |
Provided is an A/D converter that comprises: integration circuits (10, 12, 14) for executing ΔΣ modulation for which an analog signal (Vin) to be converted is used as an input signal; adders (30, 32) for outputting an addition result o...
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WO/2017/209690A1 |
Various embodiments may provide a delta sigma modulator for generating a digital output voltage. The delta sigma modulator may include a capacitance-to-voltage converter for converting a sensed continuous-in-time applied capacitance sign...
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WO/2017/203976A1 |
The present disclosure pertains to a compression encoding device and method, a decoding device and method, and a program, which enable provision of lossless compression technique at a higher compression rate. According to the present inv...
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WO/2017/190976A1 |
A bitstream converter for converting a 1-bit pulse density modulated (PDM) bitstream signal into an analog audio signal, the bitstream converter comprising: a processor configured to process the 1-bit PDM bitstream signal using a return ...
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WO/2017/187914A1 |
The present invention comprises: a wireless device 3 that receives a ΔΣ-modulated signal obtained by ΔΣ-modulating a transmission signal; and a signal processing device 2 that transmits the ΔΣ-modulated signal to the wireless devic...
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WO/2017/187917A1 |
The present invention comprises: a signal processing device 2 that transmits, via a signal cable 4, a ΔΣ-modulated signal obtained by ΔΣ-modulating a transmission signal that is an RF signal; and a wireless device 3 that transmits, v...
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WO/2017/188897A1 |
According to various embodiments, an inverter-based resistor may be provided. The inverter- based resistor may include at least one digital inverter, wherein each of the at least one digital inverter is configured to receive an input and...
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WO/2017/182272A1 |
A signal processing arrangement (100) has a signal input (SI) for connecting a capacitive sensor (CS). An amplifier circuit (AMP) is coupled between the signal input (SI) and a feedback point (CB1). A loop filter (LF) is coupled downstre...
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WO/2017/179508A1 |
Provided is an A/D converter that does not need to be equipped with a post-filter used for subsequent regeneration of the output from a modulator, that has a simplified circuit configuration, and the circuit scale of which can be reduced...
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WO/2017/154532A1 |
A problem with conventional distortion pulse shift circuits is that the output timing of a pulse signal cannot be controlled unless a reset signal is used. This pulse shift circuit is provided with: an integrator which integrates an inpu...
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WO/2017/149978A1 |
[Problem] To provide a ring oscillator capable of controlling frequency according to the delay amount of a delay element, with a structure for which fine-level frequency setting is possible. [Solution] A reference signal generation devic...
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WO/2017/134097A1 |
A variable output data rate converter circuit preferably meets performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma delta modulator circuit to qua...
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WO/2017/121682A1 |
A band-pass filter (13) is described comprising a first first-order filter stage comprising a first resistor (R1) characterised by a first impedance and connected to a first node (25), referred to as a filter input node, and, through a s...
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WO/2017/116629A1 |
In accordance with embodiments of the present disclosure, a processing system comprising may include a plurality of processing paths and a filter. The plurality of processing paths may include a first processing path and a second process...
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WO/2017/112210A1 |
Some embodiments include apparatus and methods using a first stage including an integrator, a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series w...
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WO/2017/103694A1 |
A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of comparator readouts, effectively increasing the sensitivity of the comparato...
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WO/2017/097968A1 |
An ultrasound imaging system probe comprises an imaging transducer head and a reception circuit for processing received reflected ultrasound signals. The reception circuit comprises an analogue to digital sigma delta converter which comp...
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WO/2017/086188A1 |
The objective of the present invention is to provide a sensor device equipped with an A/D converter that performs ∆ modulation or mixed modulation, with which it is not necessary to provide an impedance conversion circuit, and which is...
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WO/2017/073357A1 |
A sigma-delta analog-to-digital converter comprises a sigma-delta modulator; and an ADC filter that receives a segment of L binary samples from the sigma-delta modulator, L being a positive integer. The ADC filter includes a predictor ci...
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WO/2017/067804A1 |
The present invention concerns a device (10) for generating analogue signals comprising a current pump (12) controlled by a control code (cmd) generated by a module (11) for calculating the digital code with noise-shaping. The calculatio...
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WO/2017/064841A1 |
A current mode sigma-delta modulator comprises an input node; a comparator that compares a voltage of the input node to a reference voltage and outputs a comparison result; an integrating capacitor connected to an input of the comparator...
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WO/2017/059927A1 |
The electronic circuit (5) comprises a sigma-delta modulator (20) having a configurable resolution and a mode selector (30). The sigma-delta modulator (20) is selectively operable in at least two operation modes. The mode selector (30) i...
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WO/2017/052921A1 |
Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alter...
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WO/2017/045962A1 |
The invention describes a method of performing analog-to-digital conversion on an input signal (Pin) within a range (R1) using a sigma-delta modulator (1) comprising a feedback digital-to-analog conversion arrangement (12, 120), which me...
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WO/2017/041994A1 |
An embodiment takes the form of a method carried out by a communication device. A binary data sequence is obtained at a communication device for transmission via a Bluetooth data link configured according to an audio-codec-based Bluetoot...
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WO/2017/037880A1 |
This ΔΣ modulator uses multiple integrators. The integrators each: include multiple stages of adder sequences each formed of multiple serially-connected adders; feedback, as inputs to a first adder sequence which is the first stage of ...
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WO/2017/040812A1 |
Provided are systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is...
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WO/2017/030839A1 |
One method of processing microphone input in an ADC to determine microphone configuration is to process the microphone input signals in two processing paths, in which one processing path processes a difference between differential input ...
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WO/2017/027803A1 |
Converter circuits and methods herein describe mechanisms for converting a digital input signal to an analog output signal using a series of transmission lines. The circuits and methods described herein convert to analog signal using ver...
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WO/2017/011145A1 |
A delta-sigma modulation analog-to-digital converter (ADC) may be constructed by combining a VCO used for a first order filter with a digital loop filter used for a second or higher order of the ADC. One such ADC would include an analog ...
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WO/2017/008550A1 |
An ELD compensation circuit is used to perform ELD compensation for the ELD time of a continuous time Δ-Σ analog-to-digital converter. The circuit comprises: a delay module (200) and a compensation module (201), wherein the delay modul...
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WO/2016/199596A1 |
The present invention relates to a signal processing device, a signal processing method, and a program that make it possible to switch, using a simple configuration, a plurality of DSD signals having different sampling frequencies. An ac...
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WO/2016/197245A1 |
Systems, methods and apparatuses described herein generally provide a millimetre size package-free complementary metal–oxide–semiconductor ("CMOS") chip (referred to as a "die") for the in situ (on-site) measurement or imaging of ele...
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WO/2016/191054A1 |
An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second ...
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WO/2016/174805A1 |
Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention ...
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WO/2016/156105A1 |
The invention concerns a method and transmitter for pulse pattern generation using delta sigma modulation. First, an input signal is duplicated into a first and a second input signal part. A delta sigma modulation is performed on the fir...
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WO/2016/155825A1 |
The sigma-delta modulator arrangement (100)comprises a continuous-time sigma-delta modulator (CT_SDM)with at least one modulator stage, a digital integrator(Int_d)and a given number of switches(Sw1,…,Sw8). The switches (Sw1,…,Sw8) ar...
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WO/2016/153813A1 |
Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The i...
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WO/2016/149130A2 |
A single plate capacitance sensor includes a sensor capacitor and a reference capacitor that share common plate. A capacitance-to-digital sigma delta modulator provides separate sensor excitation and reference excitation signals to the s...
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WO/2016/142587A1 |
Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. The apparatus may include an in-phase sigma delta receiver coupled to a radio frequency input port prov...
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WO/2016/144911A1 |
In described examples, wideband capacitive sensing (10) (single-ended or differential) is based on a modulated sense (capacitance) signal. A carrier/drive signal path (23, 34, 35) modulates a reference signal (31) with a carrier signal (...
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