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WO/2022/155596A1 |
A system, method, diagnostic and container delivery system for manipulating a target, by manipulating with the quantum coherence of the target. The method includes identifying intrinsic parameters of the target and determining target-tun...
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WO/2022/147982A1 |
The present application relates to an electrode layer and a preparation method therefor, and a capacitor. The preparation method for an electrode layer comprises the following steps: forming a first electrode layer, wherein the first ele...
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WO/2022/147958A1 |
The present application relates to the technical field of semiconductors, and specifically to a method for manufacturing a capacitor structure, a capacitor structure, and a memory, used for solving the technical problem of poor performan...
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WO/2022/146486A1 |
A thin film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a TFR element connected between first and second vertically-extending TFR side contacts. The TFR element includes a base portion extendi...
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WO/2022/134847A1 |
The present invention relates to the technical field of communications. Provided are a substrate integrated with a passive device and a manufacturing method therefor. The substrate integrated with the passive device comprises a dielectri...
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WO/2022/132357A1 |
An apparatus includes: a substrate; a plurality of pillar-shaped bottom electrodes provided over the substrate; and an upper electrode covering side and top surfaces of the pillar-shaped bottom electrodes with an intervening capacitor in...
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WO/2022/132415A1 |
Some embodiments include a ferroelectric device having a ferroelectric insulative material which includes zinc. Some embodiments include a capacitor having a ferroelectric insulative material between a first electrode and a second electr...
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WO/2022/128267A1 |
A semiconductor structure, and a method of making the same includes a multiple electrode stacked capacitor containing a sequence of first metal layers interleaved with second metal layers. A quad-layer stack separates each of the first m...
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WO/2022/117565A1 |
An approach to forming a semiconductor device where the semiconductor device includes a first power rail (3A, 3B) with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling cap...
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WO/2022/118133A1 |
A capacitor structure is disclosed. The capacitor structure includes a substrate (102); a conductive layer (104) above the substrate (102); and a porous layer, above the conductive layer (104), having pores that extend perpendicularly fr...
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WO/2022/108621A1 |
A thin film resistor (TFR) module may be formed in copper interconnect in an integrated circuit device. A pair of displacement-plated TFR heads may be formed by forming a pair of copper TFR head elements (e.g., damascene trench elements)...
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WO/2022/091024A1 |
An electrical device comprising a capacitor, comprising: a substrate (100), an anodic porous oxide region (105) above the substrate, a first capacitor electrode region (111A) arranged in the anodic porous oxide region, extending in the a...
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WO/2022/093460A1 |
Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially...
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WO/2022/092449A1 |
The present invention relates to a silicon capacitor based on a thin film deposited on a three-dimensional structure, and a method for manufacturing same. More specifically, the present invention relates to: a capacitor comprising a sili...
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WO/2022/085470A1 |
This memory cell array unit according to one embodiment comprises a micro-controller which, on the basis of read/write control from a memory controller, performs reading/writing on a memory cell array by using n-bit allocated memory cell...
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WO/2022/086635A1 |
Disclosed are examples of 3D metal-insulator-metal (MIM) capacitor structures, e.g., in semiconductor packages. The disclosed 3D MIM capacitors provide high capacitance in small areas. As such, the disclosed 3D MIM capacitors may be used...
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WO/2022/083898A1 |
Various aspects relate to a functional structure having predefined properties (e.g., predefined electronic properties, e.g., a predefined crystallographic texture, e.g., a defect density in a predefined range) and methods for manufacturi...
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WO/2022/085471A1 |
A memory cell array unit according to one embodiment of the present disclosure comprises a memory cell array and a microcontroller. The memory cell array is configured by including: n assignment bits to be assigned from the memory contro...
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WO/2022/080229A1 |
A 3-dimensional electrical element 10 comprises four or more non-linear parts 11, each exhibiting non-linear current-voltage characteristics, and conductors 12 connecting the non-linear parts 11, and the non-linear parts 11 are arranged ...
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WO/2022/068324A1 |
The present disclosure belongs to the technical field of semiconductors, and provides a semiconductor structure fabrication method, a semiconductor structure, and a memory. The semiconductor structure fabrication method comprises: provid...
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WO/2022/066299A1 |
An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer ...
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WO/2022/057022A1 |
Provided are a display substrate and display apparatus, the display substrate comprising a base substrate (10), the base substrate (10) having a storage capacitor, the storage capacitor comprising: a metal layer common electrode (20); a ...
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WO/2022/055103A1 |
According to one embodiment of the present invention, a method for forming a region-selective thin film comprises: a selectivating agent supply step of supplying a selectivating agent to the inside of a chamber in which a substrate is pl...
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WO/2022/055911A1 |
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. ...
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WO/2022/052741A1 |
A capacitor structure and a method for forming same. The method comprises: forming a first capacitor (702) on a first side (701) of a wafer (501); and forming a second capacitor (901) on a second side (703) thereof. The capacitor structu...
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WO/2022/046334A1 |
Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and...
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WO/2022/047350A1 |
A galvanic isolation capacitor device (400D) includes a semiconductor substrate (402) and a PMD layer (404) over the semiconductor substrate. The PMD layer has a first thickness (Tl). A lower metal plate (412 A) is over the PMD layer and...
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WO/2022/046167A1 |
A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and...
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WO/2022/046422A1 |
Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes h...
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WO/2022/046236A1 |
At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor is...
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WO/2022/046362A1 |
Some embodiments include a transistor having an active region containing semiconductor material. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one eleme...
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WO/2022/039978A1 |
Embodiments herein are directed to methods of forming titanium nitride films suitable for use as a bulk fill material for conductive features in a semiconductor device, such as for capacitor electrodes and/or buried word lines in a dynam...
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WO/2022/034423A1 |
A semiconductor device includes an active region, a LOCOS region formed within the active region and that extends vertically above a top surface of the active region, a gate region formed above the top surface of the active region, and a...
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WO/2022/035096A1 |
A display device is provided. The display device comprises: a first electrode and a second electrode that are spaced from each other in a first direction; a plurality of light-emitting elements arranged between the first electrode and th...
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WO/2022/022030A1 |
A semiconductor structure forming method and a semiconductor structure. The semiconductor structure forming method comprises: providing a substrate (101), the substrate (101) at least comprising a conductive layer (111), the top surface ...
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WO/2022/026209A1 |
A method of forming an array of capacitors comprises forming rows and columns of horizontally- spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a...
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WO/2022/020083A1 |
Some embodiments include an integrated assembly having a row of conductive posts. The conductive posts are spaced from one another by gaps. Leaker device material extends is within at least some of the gaps. An insulative material is alo...
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WO/2022/015850A1 |
Provided are carbon-free (i.e., less than about 0.1 atomic percentage of carbon) Zr doped HfO2 films, where Zr can be up to the same level of Hf in terms of atomic percentage (i.e., 1% to 60%). The Zr doping can be achieved also by nanom...
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WO/2022/013713A1 |
An electrical device comprising: a metal barrier layer (102), an anodic porous oxide region (AAO) on the metal barrier layer, a trench (104) around the anodic porous oxide region reaching the metal barrier layer, a liner (107) at least o...
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WO/2022/007445A1 |
A method for preparing a three-dimensional capacitor, which method belongs to the technical field of semiconductors. A three-dimensional capacitor prepared by means of the method occupies a small area, such that the on-chip area utilizat...
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WO/2022/001519A1 |
A semiconductor device and a manufacturing method therefor. The semiconductor device manufacturing method comprises: providing a semiconductor substrate (300), and forming an underlying metal layer (301) on the semiconductor substrate (3...
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WO/2021/258595A1 |
A crimping-type module electrode crimping device, belonging to the technical field of rectification module processing apparatuses. The crimping device comprises: a base (1), wherein a lower fixing plate (2) is arranged on the base (1), s...
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WO/2021/260572A1 |
An electronic component (1) comprising a 3D capacitive structure includes a substrate (2) having a contoured surface (2a) comprising a plurality of wells (3) extending from the surface into the substrate body, a dielectric (5) formed ove...
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WO/2021/260541A1 |
A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer (104) disposed over a substrate (102); a conductive layer (106) disposed over the first metal layer...
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WO/2021/261868A1 |
A semiconductor device according to the technical idea of the present invention comprises: a substrate in which an active region is defined; a gate dielectric layer disposed on the active region; a gate electrode disposed on the gate die...
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WO/2021/262658A1 |
Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage no...
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WO/2021/257238A1 |
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconduc...
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WO/2021/254030A1 |
A semiconductor component, a capacitor device, and a manufacturing method for the capacitor device. The manufacturing method comprises: forming on a substrate (1) multiple storage node contact plugs (11) in an array distribution and an i...
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WO/2021/253527A1 |
An HfO2-based ferroelectric capacitor and a preparation method therefor, and an HfO2-based ferroelectric memory, relating to the technical field of microelectronics. The purpose of enlarging a storage window of the ferroelectric memory i...
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WO/2021/252118A1 |
A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx la...
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