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WO/2005/018094A1 |
A semiconductor integrated circuit device (1) includes: a transistor switch (SWA) for electrically connecting and disconnecting output of a flip-flop (FF64) of a shift register (SR1) and input of a flip-flop (FF65) of a shift register (S...
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WO/2005/006558A2 |
A frequency prescaler includes true single phase clock (TSPC) flip-flops having a logic gate such as an OR-gate embedded in an input stage. This invention is described in figure 1. A precaler (100) includes flip-flops (102, 104, 106, 108...
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WO/2004/112251A1 |
A high speed CMOS phase locked loop (PLL) (10) includes a three-state phase detection circuit having a frequency phase detector (12) coupled to a charge pump (14) for monitoring the phase differences between a reference frequency signal ...
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WO/2004/105247A1 |
A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of a reverse/non-reverse device (304). A connection device (306) is arranged on the feedback path (307). The feedback path (3...
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WO/2004/084412A1 |
A divide-by-n process is effected via a scale-by-four/n process (110, 210, 310) followed by a divide-by-four process (120, 220, 320). A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By...
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WO/2004/084411A1 |
The invention relates to a frequency divider with variable division rate, which is made using CMOS technology. The inventive divider comprises a plurality of cells (c1 to c3) which are mounted in a chain, the output of the last cell of t...
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WO/2004/077676A1 |
The invention relates to a phase-locking circuit (1, 5, 7, 14), wherein a frequency counter (10) is provided in addition to a phase divider (5) which is preferably programmable and which is arranged in the feedback path of the PLL, said ...
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WO/2004/068273A2 |
A digital counter (e.g., Fig. 1) that uses non-volatile memories (12, 14, 16, 18, …) as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter (20, 22) that keeps track ...
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WO/2004/068706A2 |
A counter for synthesizing clock signals with minimal jitter analyzes an ongoing count to determine whether the rising edge of an output clock should be triggered by the rising edge or falling edge of an input clock signal and to further...
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WO/2004/047269A2 |
Dynamic flip-flop circuit comprising pass transistors (2620.4, 2624.4) and inventers (2622.4, 2626.4, 2628.4) and its application to a gray counter.
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WO/2004/042928A1 |
The invention relates to a circuit arrangement for frequency division (50), comprising a divider chain with several frequency division stages (1 to 5). The frequency divider (1 to 5) can be switched between the divider ratios 2 and 3. At...
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WO/2004/034587A1 |
A phase-locked loop having a programmable loop bandwidth is provided. A PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-corre...
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WO/2004/032327A1 |
Techniques are described for producing a signal (120) having a desired frequency. The desired frequency can be produced to a very high precision, even when the desired frequency is very high. The techniques, in one example, represent an ...
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WO/2004/021355A2 |
An electronic device (100) has a data storage device (120) for storing N data elements, the data storage device (120) comprising a first collection (122) of data storage elements (130). The first collection (122) of data storage elements...
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WO/2004/010587A1 |
An adder (2) and a delay device (4) constitute a 20-bit input accumulator, which is connected to a signal input terminal (1). An adder (8) and a delay device (10) constitute a 9-bit input accumulator. The most significant 8 bits of outpu...
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WO/2004/006436A2 |
A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting s...
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WO/2003/105347A1 |
A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use ...
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WO/2003/094353A1 |
A high speed programmable counter architecture is disclosed (208). In accordance with an embodiment of the present invention, the high speed programmable counter includes an n bit high speed prescaler (304) and an m bit low speed counter...
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WO/2003/079551A1 |
The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler(P, P+1) and two counters (R and Q) by interleaving the division moduli. Within a given cycle, 'ones' and 'tens' are not all c...
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WO/2003/058817A1 |
A prescaler circuit comprising n DFF circuits (n≥3); a first multi-input logic gate circuit having two or more inputs; and a second multi-input logic gate circuit, wherein the output terminals of the first multi-input logic gate circui...
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WO/2003/043193A1 |
A programmable−divider provides a lower−speed transition signal to effect a synchronized load of a new divisor value during a safe−load period of the programmable−divider, such that the division occurs using either the prior divi...
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WO/2003/032495A1 |
The invention concerns a dual-mode divider counter circuit for a frequency synthesizer comprising several 1:2 dividers of asynchronous type connected in series, a phase selector block (11) interposed between two of the 1:2 dividers (10, ...
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WO/2003/021785A2 |
A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectiv...
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WO/2003/019781A2 |
Apparatus (50) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1, fvco). The apparatus (50) comprises a chain of frequency dividing cells (51-56), wherein each of the frequency div...
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WO/2003/017491A2 |
A method and apparatus for dividing a signal's frequency by a non-integer value is provided. Further, a method and apparatus for dividing a signal's frequency by a non-integer value by counting phases of the signal is provided.
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WO/2003/005588A1 |
A frequency divider device including: a divider input: a phase count and select section including: at least two phase count and select inputs each communicatively connected to the divider input, for receiving each at least one phase shif...
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WO/2002/101930A2 |
A high-speed programmable synchronous counter is disclosed. The high-speed counter includes a most-significant-bit counter synchronized with a lease-significant bit counter. The least-significant-bit counter is programmed to an initial s...
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WO/2002/093747A2 |
Apparatus (70) for generating an output signal (fdiv) whose frequency is lower than the frequency of an input signal (CK1). The apparatus (70) comprises a chain of frequency dividing cells (71-76), wherein each of the frequency dividing ...
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WO/2002/082652A2 |
A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") transmits a plurality of clock phases to a clock divider circuit which produces the desired n...
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WO/2002/080369A2 |
A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of bo...
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WO/2002/071614A1 |
A frequency synthesizer (200) is provided that allows for a half-cycle division of the synthesized frequency. In a conventional sigma-delta fractional-N frequency synthesizer, a controllable divider is configured to allow for the divisio...
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WO/2002/069499A2 |
An in-phase clock signal CLK$m(Y)I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT$m(Y)I is a clock signa...
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WO/2002/054593A2 |
A digital frequency multiplier provides no-integer frequency multiplication of an input signal. A multiplier receives the input signal and an integer multiple of the input signal. A multiplier control signal selects/toggles which signal ...
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WO/2002/052727A1 |
Apparatus comprising a frequency dividing cell (42) with a prescaler logic, an end-of-cycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency f...
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WO/2002/052728A2 |
The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regi...
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WO/2002/035706A1 |
This invention relates to a prescaler comprising a pulse swallow circuit in series connection with a divider circuit providing a fixed division ratio, wherein the pulse swallow circuit comprises the input of the prescaler and a control i...
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WO/2002/029973A2 |
A programmable divider includes a synchronous counter (202) configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices (210, ...,21N) are coupled to the sync...
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WO/2002/023725A1 |
A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of sa...
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WO/2002/017494A2 |
A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and ...
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WO/2001/093427A1 |
This invention relates to a CMOS prescaler device for frequency dividing a high frequency signal, said device having two operating modes providing two different divisional ratios and comprising: a first fixed division ratio divider havin...
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WO/2001/091298A2 |
A fractional divider divides an input frequency of a first signal (Fi) by a rational, non-integral number, which rational number is greater than one and, when written as vulgar fraction, can only be written with a denominator not equal t...
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WO/2001/084710A1 |
The power consumption of a frequency divider can effectively be reduced when the frequency of the input signal varies by more than the division factor of a divider cell in the frequency divider. A low frequency input signal requires a lo...
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WO/2001/080426A1 |
A PLL circuit comprises means (3) for generating a plurality of reference signals (fR1-fR8) of different phases, a primary divider (30) for dividing the output signal (fVCO) from a voltage-controlled oscillator (29) by a factor N1, a sec...
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WO/2001/065681A2 |
A phase-locked loop has a phase detector (501) that generates a phase difference signal, a circuit (505) that generates a phase-locked loop output signal having a frequency that is a function of the phase difference signal, a frequency d...
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WO/2001/054282A1 |
The present invention relates to a frequency divider having an adjustable divider ratio (TV). Such circuits are subject to requests for ever higher clock frequencies. For fulfilling said requests, the inventive circuit generates the outp...
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WO/2001/050610A1 |
A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite ph...
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WO/2001/045263A1 |
A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase-Lock-Loop (PLL), while simultaneously maintaining low jitter. In...
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WO/2001/033716A1 |
Non-power-of-two grey-code counters (AP1, AP4, AP5, AP6), including modulos-10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register (REG, 402, 502, 602) for storing an N-bit, e.g., 4...
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WO/2001/015323A1 |
A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer...
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WO/2001/013520A1 |
Method for frequency distribution, especially for high-frequency synthesis using a phase-regulating or frequency-regulating loop via counting device (19, 25). Frequency is adjusted by means of a control word, whereby an addend (S) for th...
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