| Document |
Document Title |
|
JP3571228B2 |
The frequency divider includes a frequency divider element (H) which forms a first intermediate signal (1) with half the frequency (f) of an input signal (IN). An intermediate divider (4/5) produces a second intermediate signal (2) with ...
|
|
JP3567309B2 |
A counter operated on the 2-phase clock which divides a lag time occurring in shift circuits into two parts, one being on the basis of a first clock and the other being on the basis of a second clock, the lag time in each part being inde...
|
|
JP3567820B2 |
|
|
JP3566342B2 |
PURPOSE: To provide a parallelly operated high-speed counter for making high- speed counting possible by parallelly operating the two counters of two system for the high-speed counting impossible by one counter. CONSTITUTION: This counte...
|
|
JP3563198B2 |
To control counting of an up-down counter circuit with two input terminals. When input signals given to two input terminals 1, 2 both set to a low level, a value of the counter is reset to '0'. When an input signal of either of the two i...
|
|
JP3563265B2 |
To attain miniaturization and low power consumption by constructing a frequency divider with a small number of transistors. A current is fed by a current source which consists of transistors D1 to D4, whose gates and sources are connecte...
|
|
JP3561657B2 |
|
|
JP3553753B2 |
To enable a PLL circuit to reduce a frequency of an operation clock that detects a pulse. A pulse detecting part 10 samples a pulse signal to be demodulated, based on an operation clock. An operation clock generating part 9 generates an ...
|
|
JP2004222212A |
To provide a counter circuit whose scale is prevented from being made large by reducing the number of gates, chip areas.The counter circuit is provided with a half adder 11, registers 12-P, 12-Q, 12-R, 12-S and a multiplexer 13-2. The ha...
|
|
JP3548925B2 |
|
|
JP2004201169A |
To accelerate an operating speed of a PLL circuit using a 4-to-1 multiplexer and to reduce power consumption thereof.The 4-to-1 multiplexer 1 for selecting one signal from among signals whose phases are 0°, 90°, 180° and 270° formed ...
|
|
JP2004519917A |
A frequency synthesizer is provided that allows for a half-cycle division of the synthesized frequency. In a conventional sigma-delta fractional-N frequency synthesizer, a controllable divider is configured to allow for the division of t...
|
|
JP2004519958A |
A programmable fractional frequency divider enables a finer resolution of output frequency than conventional integer frequency dividers. The programmable fractional frequency divider of this invention allows for the programmability of bo...
|
|
JP2004165757A |
To provide a device capable of suppressing a clock frequency to low because a circuit operates at the frequency of an input clock, and reducing the power consumption of the circuit and heat generation associated therewith.The circuit for...
|
|
JP2004517542A |
A digital frequency multiplier provides non-integer frequency multiplication of an input signal. A multiplexer receives the input signal and an integer multiple of the input signal. A multiplexer control signal selects/toggles which sign...
|
|
JP3536073B2 |
PURPOSE: To obtain the frequency divider with decimal fraction in which switchover and setting of a frequency division ratio are conducted at a high speed in order to reduce phase noise of a frequency synthesizer so as to increase a resp...
|
|
JP2004516768A |
Apparatus comprising a frequency dividing cell (42) with a prescaler logic, an end-of-cycle logic, a clock input for receiving an input clock (CKin) with frequency fn, a clock output for providing an output clock (CKout) with frequency f...
|
|
JP3522584B2 |
To surely and stably release a power saving state by providing a step for generating a first initialization signal for initializing a reference signal frequency dividing step and a step for generating a second initialization signal for i...
|
|
JP2004128767A |
To provide a flip-flop circuit capable of deciding an initial logic value in an ECL circuit.The flip-flop circuit 2 is provided with ECL circuits 11 to 14 each comprising transistor pairs whose emitters are connected. The flip-flop circu...
|
|
JP3519346B2 |
To obtain a low whole frequency division ratio by means of a high frequency division ration in a preceding frequency dividing period and the low frequency division ratio of a main frequency divider by providing a plurality of different f...
|
|
JP2004110902A |
To provide a counting circuit which permits easy changing of conditions of detected signals and is simple and small in configuration and a nonvolatile semiconductor memory which uses the same.The pulse counting circuit which counts the p...
|
|
JP3516590B2 |
To obtain a frequency divider that receives a very high frequency signal by dynamically selecting a couple of division ratios from among division ratio pairs as a function for a selection signal for the prescaler and configuring an opera...
|
|
JP3514532B2 |
PURPOSE: To minimize the deviation of an actual output frequency from a desired output frequency for the same input clock and to improve the accuracy of output clocks. CONSTITUTION: This generator is provided with a timer part 1 for gene...
|
|
JP3510903B2 |
PURPOSE: To provide a high-speed adder (provided with a subtractor) and a counter constituted of a programmable lookup table in a programmable logic device. CONSTITUTION: A conventional lookup table 10 is divided into smaller lookup tabl...
|
|
JP3508762B2 |
To provide a frequency divider circuit in which the delay time of a clock signal is hardly changed even when the frequency dividing ratio of the inputted clock signal is changed. The frequency divider circuit has a frequency dividing mea...
|
|
JP2004507824A |
A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30).The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a...
|
|
JP3504316B2 |
PURPOSE: To provide a pattern counter to be operated with multiple bits at high speed by combining plural counter devices composed of the small number of bits. CONSTITUTION: An n-bit low-order bit counter 11 and an m-bit high-order bit c...
|
|
JP3503967B2 |
PURPOSE: To make a clock frequency highest by constituting a frequency diver, so that the maximum speed of the divider may become closer to those designated to individual counters. CONSTITUTION: A 16-bit high-speed frequency divider oper...
|
|
JP2004064557A |
To reduce a layout area, and to reduce power consumption in the transition of a clock signal by reducing the number of MOS transistors of a flip flop circuit.A P channel MOS transistor 11 and an N channel MOS transistor 12 respectively c...
|
|
JP2004064183A |
To ensure the duty of an outputted 2n division clock in switching the frequency division number of the clock after setting the division number as n.An n-bit decoder circuit 103 decodes a frequency division number n preset in a memory 101...
|
|
JP2004056717A |
To provide a semiconductor device for clock generator, a system board, and a multi-phase clock generating circuit in which stable operations of a circuit is made possible and an output clock signal of a uniform duty ratio is obtained by ...
|
|
JP2004040451A |
To provide a generating circuit for pulse width modulation (PWM) signal that can faithfully generate PWM signals of the duty in a prescribed period, based on set data over the entire period.In the PWM signal generating circuit, provided ...
|
|
JP2004023599A |
To provide a frequency divider circuit for bringing a duty ratio required to produce a phase difference of 90-degrees at high frequency PSK modulation to 50%.The frequency divider circuit includes: a multiplier circuit one input signal o...
|
|
JP3489178B2 |
PURPOSE: To provide the synchronous counter which simultaneously satisfies simplification of the wiring pattern and reduction of the circuit area and realizes high-speed operation. CONSTITUTION: This synchronous counter consists of one D...
|
|
JP3485449B2 |
To provide a clock frequency dividing changeover circuit that requires a small circuit scale. A quadridecimal Johnson counter is composed of D flip-flops (DF/Fs) 31 to 37 that input a master clock as a clock, a ten frequency dividing out...
|
|
JP3482841B2 |
To output a signal whose pulse width is short even if the frequency of a clock signal to be inputted is made low by inputting a 1st clock signal or a 2nd clock signal that is opposite phase to the 1st clock signal to respective switching...
|
|
JP3468964B2 |
To prevent malfunction of a prescaler for the operation delay of a swallow counter and to enable a high speed operation. A swallow counter is provided with a malfunction prevention circuit part 42. When all the set value data A1 to A7 su...
|
|
JP2003534699A |
A fractional divider divides an input frequency of a first signal (Fi) by a rational, non-integral number, which rational number is greater than one and, when written as vulgar fraction, can only be written with a denominator not equal t...
|
|
JP2003324345A |
To realize a frequency divider which can have a frequency division ratio 'natural number/2' by using a simple circuit.The frequency divider which can have the frequency division ratio 'natural number/2' is simplified by providing a 1st b...
|
|
JP2003533084A |
The power consumption of a frequency-divider can effectively be reduced when the frequency of the input signal varies by more than the division factor of a divider cell in the frequency divider. A low frequency input signal requires a lo...
|
|
JP2003309466A |
To provide a cascadable divide-by-two binary counter circuit for use as a synchronous divider circuit in a phase lock loop.This binary counter circuit 120 is composed of a D-FF (D flip- flop) 122 and cascaded. An AND gate 124 is responsi...
|
|
JP2003298412A |
To provide a counter circuit which operates at high speed with reduced power consumption and is easily controlled.The counter circuit is composed of a plurality of counter registers including counter bits and a register including an allo...
|
|
JP2003283331A |
To provide a gray code counter which has a simple circuit constitution and facilitates designing a circuit of the desired number of bits.A gray-binary converter 20 converts output signals G0-Gn of gray codes outputted from a holder 10 to...
|
|
JP2003270367A |
To provide a timer circuit capable of greatly lowering the number of flip-flops within an allowable precision range and reducing a circuit scale as a whole.This time circuit is provided with a common counter 30 constructed by connecting ...
|
|
JP2003243979A |
To provide a power consumption reduction circuit in which holding of a degree of freedom in the optimization of logic composition due to an HDL and saving of power due to a gating clock can be simultaneously achieved.The current count va...
|
|
JP3439351B2 |
To improve the processing speed for the operation of frequency- division data by reconstituting the data of a frequency division number (N) from an N-valued data latch circuit, base on the data of the frequency division number of a dual-...
|
|
JP2003229761A |
To solve the problem of a large through-current flowing due to a maximum transition of data, while a ripple counter counts up/down, this causing a noise having adverse influences on neighboring analog circuits.The counter circuit compris...
|
|
JP3435751B2 |
PURPOSE: To provide a frequency divider which has the high frequency setting accuracy without increasing the stage number of the divider having the fractional dividing number and also can attain a PLL frequency synthesizer having a short...
|
|
JP3434627B2 |
To prevent the deterioration of the phase noises and the jitter characteristic by outputting the sine or cosine wave data equivalent to a prescribed period and using these wave data as the clock output of a rectangular wave after the ana...
|
|
JP3431754B2 |
To heighten the upper limit of clock frequency in a simple circuit constitution by using a lower digit counter of parallel carry system which can fast operate and a higher digit counter which has a simple circuit constitution despite its...
|
