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JP4114722B2 |
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JP4111932B2 |
A clock frequency divider is provided which has first to Pth (where P is an integer) sub-counters (SC1 to SCP), each capable of counting M+1 clock pulses and provided in parallel, and first to Pth clock signals (IC1 to ICP) are provided ...
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JP4111636B2 |
The oscillator 40 with cycle time correction includes a low accuracy oscillator 30A generating a clock CLK3, a counter 41 counting the clock CLK3 and cleared by activation of a clear signal CLR1, a register 42 storing a count CN of the c...
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JP2008522505A |
A phase persistent agile signal source method, apparatus, and/or computer program product provides a direct digital synthesizer (DDS) clock rate, provides a frequency tuning word (FTW) for a desired output frequency, provides a DDS updat...
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JP4106842B2 |
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JP2008520154A |
The invention relates to a method and device for providing at least a first output signal (O Q) having a frequency that is obtained through dividing a clock signal (CL 1 ) frequency by an odd integer. A digital value is shifted into a se...
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JP4098785B2 |
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JP2008131071A |
To provide a gray code counter, where the number of delay flip-flops is reduced and current consumption is reduced.The gray code counter has four DFFs 11, 12, 13, 14 for holding respective bits Q3, Q2, Q1, Q0 of a gray code, a reference ...
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JP2008131560A |
To provide a frequency divider circuit which is stable in operation and low in jitter in a high-speed operation.The frequency divider circuit comprises: a D-type flip-flop 3 capable of outputting a frequency dividing signal 202 synchroni...
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JP2008124966A |
To provide a clock frequency-divider circuit capable of generating frequency-dividing clocks of various frequency-dividing ratios, without deviating phase relationship among them.Frequency-division counters 10-a to 10-c are periodically ...
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JP2008123402A |
To provide a variable clock generation circuit that generates a dividing clock at an arbitrary duty ratio while generating an arbitrary dividing clock so as to dynamically change a dividing frequency and a duty ratio of the dividing cloc...
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JP2008122159A |
To synchronize a divided clock signal with the clock signal before being divided.A clock generating circuit 1 and a synchronous circuit section 2 are formed in a semiconductor integrated circuit 30. The clock generating circuit 1 is sync...
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JP4086046B2 |
To prevent gradual degradation in the level of a signal to be inputted from each stage of a shift register to the next stage. A first stage RS1 (1) comprises five n-MOSs 201, 202, 203, 205 and 206. When the level of a signal Φ1 becomes ...
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JP2008109563A |
To provide a counter in which a delay time from a clock to a change in bits of a count value is reduced even when there are a number of bits of the count value, and power consumption is reduced.A clock gating control circuit 3 is interpo...
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JP4084176B2 |
A phase splitter circuit includes a first signal transfer path for receiving an input signal to output a first output signal, a second signal transfer path for receiving the input signal to output a second output signal having an inverte...
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JP4081674B2 |
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JP4077483B2 |
A feedback path ( 307 ) is formed between an output ( 310 c) of a fixed divider ( 305 ) and a control terminal ( 310 b) of an inverting/noninverting unit ( 304 ). A connection device ( 306 ) is arranged on the feedback path ( 307 ). The ...
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JP2008510339A |
A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(1), . . . , SA(N); SB(1), . . . , SB(N)). One multi-state circuit (MSCA) switch...
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JP2008510428A |
A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a ...
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JP2008509589A |
A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clo...
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JP4063001B2 |
A multi-phase clock generation circuit includes a clock generation circuit, first frequency divider circuit, first clock selection circuit, second to nth frequency divider circuits, second to nth clock selection circuits, and clock selec...
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JP4044819B2 |
The dual-modulus prescaler circuit for a frequency includes several dividers-by-two of the asynchronous type, connected in series, a phase selector unit (11) inserted between two of the dividers-by-two (10, 12a) and a control unit for su...
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JP4044020B2 |
The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct sign...
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JP2008017287A |
To provide an inexpensive RC calibration circuit in which a calibration time is short.This RC calibration circuit generates a frequency-division signal VIN by dividing frequency of a reference clock signal RefCLK into two, and charges a ...
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JP2008005446A |
To solve the problem of increase in size and cost of a frequency divider for outputting a plurality of output signals which differ in division ratios requires a plurality of frequency divider circuits more than the number of division rat...
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JP4028147B2 |
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JP4015232B2 |
A prescaler which can be used in a PLL includes a counter section and an extender section. The counter section has a pair of staged, synchronous flip-flops which generate a frequency divided signal by frequency dividing an input oscillat...
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JP2007300450A |
To provide a clock-generating circuit for generating a plurality of clocks at low cost by saving power consumption without having to use a PLL, and to provide an information-reproducing device, and an electronic apparatus, etc. The clock...
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JP2007294484A |
To improve the characteristics of a semiconductor integrated device for processing high-speed signals. Flip-flop circuits 21-25 for composing a prescaler 16 and NAND circuits 26-29 are arranged in two parallel rows on a semiconductor sub...
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JP3998217B2 |
A counter system has a first counter seeded by several input signals and a second counter seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an interlea...
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JP2007529179A |
Frequency dividers (2) comprising sections (21-27) are provided with basic sections of a first type (21,23,24) for dividing frequency signals (f") by adjustable numbers in dependence of adjustment signals (p") and in dependence of contro...
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JP3993717B2 |
A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clo...
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JP2007266820A |
To provide a register circuit and electric equipment using the register circuit, capable of increasing noise tolerance without delaying an output response to a regular signal input. A register circuit 1 includes a register portion 10 hav...
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JP2007221587A |
To set the duty ratio of the output signal of a variable frequency divider to an arbitrary ratio. The variable frequency divider for outputting a frequency-divided clock by dividing an input clock by a preset frequency division ratio inc...
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JP2007214960A |
To obtain low power consumption while operation speed is kept unchanged. In a toggle type flip-flop circuit (TFF), each signal of an output terminal (out) and an inverse output terminal (outb) latched at latch portions 22A, 22B are conve...
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JP2007215213A |
To provide a method for multiple-phase clock generation. In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired ...
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JP3958322B2 |
To improve both of rising characteristics and falling characteristics of an output signal in a flip-flop, and to reduce the signal delay of a shift register constituted by this flip-flop. A latch unit 22 has a latch circuit for latching ...
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JP2007522712A |
A non-quasistatic MOS frequency divider circuit uses a phase lock loop configuration including an antenna coil to induce a differential input signal, an antenna resonating capacitor, a rectifier, a voltage controlled ring oscillator, a p...
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JP2007202151A |
To provide an integrated circuit for asynchronous serial data transmission with a bit length counter. The present invention relates to an integrated circuit (7) for asynchronous serial data transmission having a structure for constitutin...
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JP3956768B2 |
To solve a problem that a frequency not suitable for a task is often generated with a clock generator which generates clocks of a plurality of frequencies, and that useless power is consumed in that event. The clock generator includes: a...
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JP2007194976A |
To provide an elastic store circuit capable of correcting phase difference between input and output timings without stopping input data or output data. A phase stability monitoring portion 19 monitors phase difference and stability of a ...
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JP3952576B2 |
To a provide a controller capable of improving processing efficiency without using a software timer and performing high-speed processing. Count time data T1 are inputted from a CPU 1 to a programmable counter circuit 21, and output data ...
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JP3949995B2 |
To provide a counter circuit capable of forming a plurality of pulse signals of different periods, without increasing the circuit scale. The counter circuit comprises an initial value register single port RAM 5, having initial value regi...
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JP2007173971A |
To provide an analog frequency divider having a wide operational frequency bandwidth.A parallel circuit of an inductor L1 and a resistor R1 is connected as a load between a power supply voltage VDD and the drain of an MOS transistor TR1,...
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JP3940877B2 |
To provide a pulse output device that eliminates the need for error correction of an oscillation frequency and can realize synchronization with an execution period of (input data from) an external processing unit, such as a CPU and that ...
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JP3935901B2 |
To provide a programmable low-power high-frequency divider circuit. A fast latch includes: a NAND stage adapted to receive a clock signal and a data input signal; a clocked inverter stage wherein a first input of the clocked inverter sta...
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JP3937686B2 |
To provide a ripple counter that corrects the count between circuits at different operating speed on the basis of prescribed correction data, and a counter correction method in the ripple counter. The ripple counter is provided with a bi...
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JP2007515821A |
The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (...
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JP3930773B2 |
To provide a frequency correction circuit for precisely correcting a clock signal of an oscillation frequency with a simple structure without adjusting the oscillation frequency in an oscillation circuit. Into the TBC(time-base counter)1...
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JP2007133527A |
To make it possible to set the frequency-division rate of each clock signal, and to switch the frequency-division rate of the clock signal based on the set frequency-division rate to output a clock signal in a clock generation circuit fo...
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